US5686356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conductor reticulation for improved device planarity
Assignee: Texas Instruments Inc
•
Filing: 1994-09-30
•
Granted: 1997-11-11
•
Expires: 2014-09-30
Abstract
Abstract A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.
Inventors
- 👤 Manoj Kumar Jain
- 👤 Michael Francis Chisholm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10P; H10P95/00; H10P95/06; H10P95/062; H10W20/01; H10W20/031; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
138 words
A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising: (a) depositing a layer of conducting material on a substrate; (b) removing said layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) depositing an insulating seed layer over said conductor and said substrate; and (e) forming an insulating layer of silicon dioxide over said conductor and said substrate by a method of simultaneous CVD and back-sputtering.
Claim 2
Independent Claim
138 words
A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising: (a) depositing a layer of conducting material on a substrate; (b) removing said layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) depositing an insulating seed layer over said conductor and said substrate; and (e) forming an insulating layer of silicon dioxide over said conductor and said substrate by a method of simultaneous CVD and back-sputtering.
Claim 3
Dependent Claim
20 words
The method of claim 1, further comprising depositing and patterning a second layer of conducting material overlying said insulating layer.
Claim 4
Dependent Claim
23 words
The method of claim 1, further comprising depositing a CVD insulating layer over said conductor and said substrate, subsequent to forming step (d).
Claim 5
Dependent Claim
12 words
The method of claim 1, further comprising chemical-mechanical polishing said insulating layer.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein said conducting segments are formed to minimum design rule specifications for said semiconductor device.
Claim 7
Dependent Claim
13 words
The method of claim 1, wherein steps (b) and (c) are performed simultaneously.
Claim 8
Independent Claim
172 words
A method of forming a planarized insulated interconnection layer on a semiconductor device, said method comprising: (a) depositing a first layer of conducting material on a substrate; (b) removing sections of said first layer of conducting material in a first pattern, thereby forming a plurality of conducting regions, at least one of said conducting regions being a reticulated conductor, said reticulated conductor comprising a set of integrally-formed conducting segments which provide multiple conducting paths between opposing ends of said reticulated conductor; (c) depositing one or more insulating layers over said conducting regions and said substrate, at least one of said insulating layers deposited by a method of simultaneous deposition and back-sputtering; and (d) depositing and patterning a second layer of conducting material over a top surface of said insulating layers, whereby said top surface of a portion of said insulating layer in the immediate vicinity of said reticulated conductor have improved planarization as compared to a top surface of a similar insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.
Claim 9
Independent Claim
172 words
A method of forming a planarized insulated interconnection layer on a semiconductor device, said method comprising: (a) depositing a first layer of conducting material on a substrate; (b) removing sections of said first layer of conducting material in a first pattern, thereby forming a plurality of conducting regions, at least one of said conducting regions being a reticulated conductor, said reticulated conductor comprising a set of integrally-formed conducting segments which provide multiple conducting paths between opposing ends of said reticulated conductor; (c) depositing one or more insulating layers over said conducting regions and said substrate, at least one of said insulating layers deposited by a method of simultaneous deposition and back-sputtering; and (d) depositing and patterning a second layer of conducting material over a top surface of said insulating layers, whereby said top surface of a portion of said insulating layer in the immediate vicinity of said reticulated conductor have improved planarization as compared to a top surface of a similar insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.
Claim 10
Dependent Claim
52 words
The method of claim 7, further comprising, before step (d), chemical mechanical polishing said top surface of said insulating layers, whereby said insulating layer overlying said reticulated conductor has a higher polish rate as compared to the polish rate of the insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.
Claim 11
Dependent Claim
17 words
The method of claim 7, wherein step (c) comprises depositing silicon dioxide by simultaneous CVD and back-sputtering.
Claim 12
Dependent Claim
20 words
The method of claim 9, wherein said CVD and back-sputtering step uses constituent gasses silane, O 2 , and argon.
Claim 13
Independent Claim
151 words
A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising: (a) depositing a first layer of conducting material on a substrate; (b) removing said first layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said first layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) forming an insulating layer over said conductor and said substrate by a deposition method which selectively planarizes features in order of smallest to largest based on minimum horizontal dimension; and (e) depositing and patterning a second layer of conducting material overlying said insulating layer.
Claim 14
Independent Claim
151 words
A method of constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device, said method comprising: (a) depositing a first layer of conducting material on a substrate; (b) removing said first layer of conducting material in a circumscribing region upon said substrate, thereby defining a location for and peripheral walls for said conductor; (c) removing said first layer of conducting material from at least one region within said circumscribing region to form internal and/or notch walls for said conductor, thereby dividing current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor; (d) forming an insulating layer over said conductor and said substrate by a deposition method which selectively planarizes features in order of smallest to largest based on minimum horizontal dimension; and (e) depositing and patterning a second layer of conducting material overlying said insulating layer.
Claim 15
Dependent Claim
24 words
The method of claim 11, wherein said forming an insulating layer step comprises depositing silicon dioxide by a method of simultaneous CVD and back-sputtering.
Claim 16
Dependent Claim
33 words
The method of claim 12, further comprising depositing an insulating seed layer over said conductor and said substrate, prior to said depositing silicon dioxide by a method of simultaneous CVD and back-sputtering step.
Claim 17
Dependent Claim
23 words
The method of claim 11, further comprising depositing a CVD insulating layer over said conductor and said substrate, subsequent to forming step (d).
Claim 18
Dependent Claim
12 words
The method of claim 11, further comprising chemical-mechanical polishing said insulating layer.
Claim 19
Dependent Claim
20 words
The method of claim 11, wherein said conducting segments are formed to minimum design rule specifications for said semiconductor device.
Claim 20
Dependent Claim
13 words
The method of claim 11, wherein steps (b) and (c) are performed simultaneously.
Claim 21
Dependent Claim
17 words
The method of claim 7, wherein at least one of said conducting regions is a non-reticulated conductor.
References Cited (Backward Citations)
JPS5745259A
Cited
US4625227A
Cited
JPS57207353A
Cited
US4797375A
Cited
GB2173822A
Cited
JPS62296447A
Cited
US5089442A
Cited
JPH04192522A
Cited
JPH053164A
Cited
US5270264A
Cited
US5234868A
Cited
US5272117A
Cited
US5494854A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |