US4797375A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication of metal interconnect for semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1987-04-09
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Granted: 1989-01-10
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Expires: 2007-04-09
Abstract
Abstract Disclosed is a method of fabricating a semiconductor device comprising the step of defining metal interconnect features in a metal layer so that a metal feature having a size substantially larger than a predetermined feature size comprises an array of metal features. Each of the metal features in the array has a size not substantially larger than the predetermined feature size.
Inventors
- 👤 David J. Brownell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:54
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
138 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than a predetermined feature size in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and bias sputtering an insulating layer over said metal features, wherein said predetermined feature size is such that the surface of said insulating layer opposite said upper surface will be substantially planar.
Claim 2
Independent Claim
138 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than a predetermined feature size in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and bias sputtering an insulating layer over said metal features, wherein said predetermined feature size is such that the surface of said insulating layer opposite said upper surface will be substantially planar.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said predetermined feature size is ten microns.
Claim 4
Dependent Claim
59 words
The method of claim 1 further including forming a connecting metal directly on said upper surface, wherein said connecting metal is substantially the same thickness as said metal features and at every point on said connecting metal said connecting metal is not substantially larger than said predetermined feature size in at least one direction parallel to said upper surface.
Claim 5
Dependent Claim
11 words
The method of claim 1 wherein said upper surface is metal.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein said upper surface is a semiconductor material.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said upper surface is a dielectric.
Claim 8
Independent Claim
128 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than ten microns in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and forming an insulating layer over said metal features so that the surface of said insulating layer opposite said upper surface is substantially planar.
Claim 9
Independent Claim
128 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than ten microns in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and forming an insulating layer over said metal features so that the surface of said insulating layer opposite said upper surface is substantially planar.
Claim 10
Dependent Claim
11 words
The method of claim 7 wherein said upper surface is metal.
Claim 11
Dependent Claim
13 words
The method of claim 7 wherein said upper surface is a semiconductor material.
Claim 12
Dependent Claim
12 words
The method of claim 7 wherein said upper surface is a dielectric.
Claim 13
Dependent Claim
14 words
The method of claim 7 wherein said insulating layer is formed by bias sputtering.
Claim 14
Independent Claim
145 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, all from the same layer of metal, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than a predetermined feature size in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and bias sputtering an insulating layer over said metal features, wherein said predetermined feature size is such that the surface of said insulating layer opposite said upper surface will be substantially planar.
Claim 15
Independent Claim
145 words
A method of forming a substantially planar insulating layer over metal features on a semiconductor device, wherein said semiconductor device has an upper surface which is substantially planar, comprising the steps of: forming a plurality of said metal features directly on said upper surface, all from the same layer of metal, said metal features all being of substantially the same thickness, wherein at every point on each of said metal features, said metal feature is not substantially larger than a predetermined feature size in at least one direction parallel to said upper surface and wherein at least two of said metal features will operate together to perform the same function on said device; and bias sputtering an insulating layer over said metal features, wherein said predetermined feature size is such that the surface of said insulating layer opposite said upper surface will be substantially planar.
Claim 16
Dependent Claim
13 words
The method of claim 1 wherein said predetermined feature size is ten microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |