Patent US5686344A successfully refreshed from Google Patents.
US5686344A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device isolation method for semiconductor device
Assignee: SK Hynix Inc
•
Filing: 1996-01-04
•
Granted: 1997-11-11
•
Expires: 2016-01-04
Abstract
Abstract An improved device isolation method for a semiconductor device capable of independently and compatibly providing an isolation film in the interior of well and an isolation film between wells during a consistent process, so that latch-up characteristic can be improved even in a device requiring a design rule of below 0.5 μm, which includes a first step which combines a second step which forms a device isolation film within a well and a third step which forms a device isolation film between wells, the second and third steps being compatible to each other during the same step.
Inventors
- 👤 Chang-Jae Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0128; H10W10/041; H10W10/10; H10W10/13; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
91 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film, a silicon film, and a nitride film on the from surface, including the trench, of said substrate in order; a third step which selectively removes said nitride film of a field region; and a fourth step which develops an isolation film in the field region using a thermal oxidation.
Claim 2
Independent Claim
91 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film, a silicon film, and a nitride film on the from surface, including the trench, of said substrate in order; a third step which selectively removes said nitride film of a field region; and a fourth step which develops an isolation film in the field region using a thermal oxidation.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said silicon film is formed with either a polycrystal silicon or an amorphous silicon.
Claim 4
Dependent Claim
38 words
The method of claim 1, wherein said device isolation method of a semiconductor device further includes an ion insertion step which is directed to performing a channel stop ion doping with respect to the bottom of the trench.
Claim 5
Dependent Claim
34 words
The method of claim 1, wherein said device isolation method of a semiconductor device further includes a step which removes the silicon film of the field region with a mask of the nitride film.
Claim 6
Dependent Claim
35 words
The method of claim 4, wherein during said silicon removing step, a side wall spacer forming of the silicon film is formed at a side wall of the thermal oxide film by an etching back.
Claim 7
Independent Claim
119 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film and a nitride film on the front surface, including said trench, of said substrate in order; a third step which selectively removes said nitride film of a field region; a fourth step which develops an isolation film in said field region through a first thermal oxidation; a fifth step which deposits a CVD silicon film and etches back it; and a sixth step which develops an isolation film in the field region through a second thermal oxidation.
Claim 8
Independent Claim
119 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film and a nitride film on the front surface, including said trench, of said substrate in order; a third step which selectively removes said nitride film of a field region; a fourth step which develops an isolation film in said field region through a first thermal oxidation; a fifth step which deposits a CVD silicon film and etches back it; and a sixth step which develops an isolation film in the field region through a second thermal oxidation.
Claim 9
Dependent Claim
20 words
The method of claim 6, wherein said silicon film is formed with either a polycrystal silicon or an amorphous silicon.
Claim 10
Dependent Claim
52 words
The method of claim 6, wherein said device isolation method of a semiconductor device further includes an ion insertion step which is directed to performing a channel stop ion doping with respect to the bottom of the trench after either the step of trench formation of the step of first thermal oxidation.
Claim 11
Dependent Claim
23 words
The method of claim 8, wherein said third step is directed to substantially removing the nitride film at the bottom of the trench.
Claim 12
Independent Claim
101 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film and a nitride film on the front surface, including the trench, of the substrate in order; a third step which selectively removes the nitride film in a field region; a fourth step which develops an isolation film in said field region through a thermal oxidation; and a fifth step which deposits a CVD insulation film and etches back it.
Claim 13
Independent Claim
101 words
A device isolation method for a semiconductor device, comprising the steps of: a first step which forms a trench at a well boundary of a semiconductor substrate having an n-well and a p-well; a second step which forms a thermal oxide film and a nitride film on the front surface, including the trench, of the substrate in order; a third step which selectively removes the nitride film in a field region; a fourth step which develops an isolation film in said field region through a thermal oxidation; and a fifth step which deposits a CVD insulation film and etches back it.
Claim 14
Dependent Claim
38 words
The method of claim 10, wherein said device isolation method of a semiconductor device further includes an ion insertion step which is directed to performing a channel stop ion doping with respect to the bottom of the trench.
Claim 15
Dependent Claim
23 words
The method of claim 10, wherein said third step is directed to substantially removing the nitride film of the bottom of the trench.
Claim 16
Dependent Claim
16 words
The method of claim 1, wherein the trench is formed to a depth of 4.0-5.0 μm.
Claim 17
Dependent Claim
30 words
The method of claim 1, wherein the thermal oxide film is formed in a dry O 2 environment at about 900° C., and to a thickness of about 150 Å.
Claim 18
Dependent Claim
26 words
The method of claim 1, wherein the silicon film is formed with a low pressure chemical vapor deposition and to a thickness of about 1000 Å.
Claim 19
Dependent Claim
23 words
The method of claim 1, wherein the step of selectively removing the nitride film is performed by using CF 3 /CF 4 .
Claim 20
Dependent Claim
33 words
The method of claim 1, wherein the isolation film is formed to have a thickness of about 4000 Å through a thermal oxide process at an environment of H 2 /O 2 .
Claim 21
Dependent Claim
25 words
The method of claim 3, wherein the ion insertion step is performed at a condition of about 5.0×10 13 ions/cm 2 and about 40 KeV.
Claim 22
Dependent Claim
41 words
The method claim 6, wherein the step of the second thermal oxidation is performed at an environment of about 1000° C. and H 2 /O 2 , and the isolation film is formed to have a thickness of about 4000 Å.
References Cited (Backward Citations)
JPS61137338A
Cited
US4766090A
Cited
US4994406A
Cited
US5130268A
Cited
US5112772A
Cited
US5455194A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |