Patent US5684948A successfully refreshed from Google Patents.
US5684948A
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Memory management circuit which provides simulated privilege levels
Assignee: National Semiconductor Corp
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Filing: 1995-09-01
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Granted: 1997-11-04
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Expires: 2015-09-01
Abstract
Abstract A memory management unit provides security functions for a processor which has no specialized hardware support for a memory management unit. An exception security system is provided for use with an exception-capable processor. In an unsecure mode, the processor responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and executes an exception processing routine indicated by the unprotected exception information. Secure exception information register circuitry is provided in the memory management unit that holds a protected copy of exception information. Exception detection circuitry within the memory management unit detects an exception and causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry. Thus, the processor executes an exception routine indicated by the protected copy of the exception information and not an exception routine indicated by the unprotected exception information. In order to simulate processor privilege levels for each of a plurality of processor address space segments, current privilege level circuitry holds a current privilege level access indication, and programmable circuitry associated with each of the address space segments holds a privilege level access indication associated that address space segment. Access validation circuitry determines which of the address space segments is being accessed by the processor and compares the current privilege level access indication with the privilege level access indication associated with the address space segment being addressed. The access validation circuitry includes violation indication means, accessible by the processor, that indicates a result of the comparison. Preferably, current privilege level circuitry is provided which holds a current privilege level indication and which also includes stack circuitry that holds a plurality of security level indications.
Inventors
- 👤 James Scott Johnson
- 👤 Tim Short
- 👤 Gideon Intrater
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:19
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/073; G06F11/0721; G06F11/0793; G06F12/00; G06F12/14; G06F12/1458; G06F12/1491; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
192 words
An exception security circuit for use with an exception-capable processor, wherein the processor, in an unsecure mode, responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and by executing an exception processing routine indicated by the unprotected exception information, the exception security unit comprising: secure exception information register circuitry that holds a protected copy of the exception information; exception detection circuitry that detects an exception and that causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry, such that the processor executes an exception routine indicated by the protected copy of the exception information; current security level circuitry for holding a current security mode indication; stack circuitry for holding a plurality of security level indications; and exception start detection circuitry for detecting an exception and, in response thereto, for pushing the current security mode indication onto the stack circuitry and for setting the indication of the current security level to a predetermined level.
Claim 2
Dependent Claim
192 words
An exception security circuit for use with an exception-capable processor, wherein the processor, in an unsecure mode, responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and by executing an exception processing routine indicated by the unprotected exception information, the exception security unit comprising: secure exception information register circuitry that holds a protected copy of the exception information; exception detection circuitry that detects an exception and that causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry, such that the processor executes an exception routine indicated by the protected copy of the exception information; current security level circuitry for holding a current security mode indication; stack circuitry for holding a plurality of security level indications; and exception start detection circuitry for detecting an exception and, in response thereto, for pushing the current security mode indication onto the stack circuitry and for setting the indication of the current security level to a predetermined level.
Claim 3
Dependent Claim
40 words
An exception security circuit as in claim 1, and further comprising exception end detection circuitry for detecting an end to exception processing and for popping the current security level indication from the stack circuitry into the current security level circuitry.
Claim 4
Dependent Claim
29 words
An exception security circuit as in claim 2, wherein the exception end detection circuitry detects the end to exception processing by detecting a non-sequential instruction fetch of the processor.
Claim 5
Dependent Claim
199 words
An exception security circuit for use with an exception-capable processor, wherein the processor, in an unsecure mode, responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and by executing an exception processing routine indicated by the unprotected exception information, the exception security unit comprising: secure exception information register circuitry that holds a protected copy of the exception information; exception detection circuitry that detects an exception and that causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry, such that the processor executes an exception routine indicated by the protected copy of the exception information; programmable circuitry associated with each of a plurality of processor-addressable memory space blocks for holding a corresponding privilege indication associated with that memory space block; and access validation circuitry that determines which of said memory space segments is being addressed by the processor and that compares the current privilege level access indication with the privilege level access indication associated with the memory space segment being addressed.
Claim 6
Dependent Claim
199 words
An exception security circuit for use with an exception-capable processor, wherein the processor, in an unsecure mode, responds to an exception by retrieving unprotected exception information from generally accessible exception information register circuitry and by executing an exception processing routine indicated by the unprotected exception information, the exception security unit comprising: secure exception information register circuitry that holds a protected copy of the exception information; exception detection circuitry that detects an exception and that causes the secure exception information register circuitry to provide the protected copy of the exception information to the processor in place of the unprotected exception information which would otherwise be provided to the processor from the generally accessible exception information register circuitry, such that the processor executes an exception routine indicated by the protected copy of the exception information; programmable circuitry associated with each of a plurality of processor-addressable memory space blocks for holding a corresponding privilege indication associated with that memory space block; and access validation circuitry that determines which of said memory space segments is being addressed by the processor and that compares the current privilege level access indication with the privilege level access indication associated with the memory space segment being addressed.
Claim 7
Dependent Claim
23 words
The exception security circuit of claim 4, wherein said access validation circuitry includes violation indication means that indicates a result of the comparison.
Claim 8
Dependent Claim
192 words
An interrupt security circuit for use with an interrupt-capable processor, wherein the processor, in an unsecure mode, responds to an interrupt by retrieving unprotected interrupt information from generally accessible interrupt information register circuitry and by executing an interrupt processing routine indicated by the unprotected interrupt information, the interrupt security unit comprising: secure interrupt information register circuitry that holds a protected copy of the interrupt information; interrupt detection circuitry that detects an interrupt and that causes the secure interrupt information register circuitry to provide the protected copy of the interrupt information to the processor in place of the unprotected interrupt information which would otherwise be provided to the processor from the generally accessible interrupt information register circuitry, such that the processor executes an interrupt routine indicated by the protected copy of the interrupt information; current security level circuitry for holding a current security mode indication; stack circuitry for holding a plurality of security level indications; and interrupt start detection circuitry for detecting an interrupt and, in response thereto, for pushing the current security mode indication onto the stack circuitry and for setting the indication of the current security level to a predetermined level.
Claim 9
Dependent Claim
192 words
An interrupt security circuit for use with an interrupt-capable processor, wherein the processor, in an unsecure mode, responds to an interrupt by retrieving unprotected interrupt information from generally accessible interrupt information register circuitry and by executing an interrupt processing routine indicated by the unprotected interrupt information, the interrupt security unit comprising: secure interrupt information register circuitry that holds a protected copy of the interrupt information; interrupt detection circuitry that detects an interrupt and that causes the secure interrupt information register circuitry to provide the protected copy of the interrupt information to the processor in place of the unprotected interrupt information which would otherwise be provided to the processor from the generally accessible interrupt information register circuitry, such that the processor executes an interrupt routine indicated by the protected copy of the interrupt information; current security level circuitry for holding a current security mode indication; stack circuitry for holding a plurality of security level indications; and interrupt start detection circuitry for detecting an interrupt and, in response thereto, for pushing the current security mode indication onto the stack circuitry and for setting the indication of the current security level to a predetermined level.
Claim 10
Dependent Claim
40 words
An interrupt security circuit as in claim 6, and further comprising interrupt end detection circuitry for detecting an end to interrupt processing and for popping the current security level indication from the stack circuitry into the current security level circuitry.
Claim 11
Dependent Claim
29 words
An interrupt security circuit as in claim 7, wherein the interrupt end detection circuitry detects the end to interrupt processing by detecting a non-sequential instruction fetch of the processor.
Claim 12
Dependent Claim
199 words
An interrupt security circuit for use with an interrupt-capable processor, wherein the processor, in an unsecure mode, responds to an interrupt by retrieving unprotected interrupt information from generally accessible interrupt information register circuitry and by executing an interrupt processing routine indicated by the unprotected interrupt information, the interrupt security unit comprising: secure interrupt information register circuitry that holds a protected copy of the interrupt information; interrupt detection circuitry that detects an interrupt and that causes the secure interrupt information register circuitry to provide the protected copy of the interrupt information to the processor in place of the unprotected interrupt information which would otherwise be provided to the processor from the generally accessible interrupt information register circuitry, such that the processor executes an interrupt routine indicated by the protected copy of the interrupt information; programmable circuitry associated with each of a plurality of processor-addressable memory space blocks for holding a corresponding privilege indication associated with that memory space block; and access validation circuitry that determines which of said memory space segments is being addressed by the processor and that compares the current privilege level access indication with the privilege level access indication associated with the memory space segment being addressed.
Claim 13
Dependent Claim
199 words
An interrupt security circuit for use with an interrupt-capable processor, wherein the processor, in an unsecure mode, responds to an interrupt by retrieving unprotected interrupt information from generally accessible interrupt information register circuitry and by executing an interrupt processing routine indicated by the unprotected interrupt information, the interrupt security unit comprising: secure interrupt information register circuitry that holds a protected copy of the interrupt information; interrupt detection circuitry that detects an interrupt and that causes the secure interrupt information register circuitry to provide the protected copy of the interrupt information to the processor in place of the unprotected interrupt information which would otherwise be provided to the processor from the generally accessible interrupt information register circuitry, such that the processor executes an interrupt routine indicated by the protected copy of the interrupt information; programmable circuitry associated with each of a plurality of processor-addressable memory space blocks for holding a corresponding privilege indication associated with that memory space block; and access validation circuitry that determines which of said memory space segments is being addressed by the processor and that compares the current privilege level access indication with the privilege level access indication associated with the memory space segment being addressed.
Claim 14
Dependent Claim
23 words
The interrupt security circuit of claim 9, wherein said access validation circuitry includes violation indication means that indicates a result of the comparison.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |