Hermetic chip and method of manufacture

Claim 2

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, a peripheral edge, and a plurality of street areas thereon forming areas therebetween on the semiconductor substrate, the semiconductor wafer substrate having portions thereof removed in the plurality of street areas thereof; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate in the areas formed therebetween by the plurality of street areas on the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by the portions of the semiconductor wafer substrate removed from the street areas of the semiconductor wafer substrate, each semiconductor device having at least one bond pad formed thereon and a plurality of peripheral edges formed by the portions of the semiconductor wafer substrate removed in the plurality of street areas; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate; and a second coating covering the second side of the semiconductor wafer substrate and substantially filling the portions of the street areas of the semiconductor wafer substrate which have been removed thereby separating areas of the semiconductor wafer substrate from other areas thereof.

Claim 3

The semiconductor wafer of claim 1, wherein the first coating further comprises: a coating on the first side of the semiconductor wafer substrate covering the plurality of semiconductor devices formed thereon except for the at least one bond pad formed on each semiconductor device.

Claim 4

The semiconductor wafer of claim 2, further comprising: a plurality of metal circuits located on the first coating on the first side of the semiconductor wafer substrate, at least one of the plurality of metal circuits being connected to the at least one bond pad of each semiconductor device.

Claim 5

The semiconductor wafer of claim 3, wherein the plurality of metal circuits further comprise: a plurality of metal circuits located on the first coating on the first side of the semiconductor wafer substrate, at least one of the plurality of metal circuits being connected to the at least one bond pad of each semiconductor device, the at least one metal circuit connected to the at least one bond pad of each of the semiconductor devices engaging the bond pad to which it is connected and engaging the first coating on the first side of the semiconductor wafer substrate located around the at least one bond pad of each semiconductor device.

Claim 6

The semiconductor wafer of claim 4, wherein the plurality of metal circuits further comprise: the at least one metal circuit connected to the at least one bond pad of each of the semiconductor devices substantially sealingly engaging the bond pad to which it is connected and substantially sealingly engaging the first coating on the first side of the semiconductor wafer substrate located around the at least one bond pad of each semiconductor device.

Claim 7

The semiconductor of claim 4, wherein the plurality of metal circuits further comprise: the at least on metal circuit connected to the at least one bond pad of each of the semiconductor devices substantially hermetically sealingly engaging the bond pad to which it is connected and substantially hermetically sealingly engaging the first coating on the first side of the semiconductor wafer substrate located around the at least one bond pad of each semiconductor device.

Claim 8

The semiconductor wafer of claim 1, wherein the second coating further comprises: a coating engaging the plurality of peripheral edges of each semiconductor device.

Claim 9

The semiconductor wafer of claim 7, further comprising: a plurality of metal circuits located on the first coating on the first side of the semiconductor wafer substrate, at least one of the plurality of metal circuits being connected to the at least one bond pad of each semiconductor device.

Claim 10

The semiconductor wafer of claim 8, wherein the plurality of metal circuits further comprise: the at least on metal circuit connected to the at least one bond pad of each of the semiconductor devices engaging the bond pad to which it is connected and engaging the first coating on the first side of the semiconductor wafer substrate located around the at least one bond pad of each semiconductor device.

Claim 11

The semiconductor wafer of claim 1, wherein the second coating further comprises: a coating substantially sealing engaging the plurality of peripheral edges of each semiconductor device formed by the removal of portions of the street areas of the semiconductor wafer substrate.

Claim 12

The semiconductor wafer of claim 1, wherein the second coating further comprises: a coating substantially hermetically sealingly engaging the plurality of peripheral edges of each semiconductor device formed by the removal of portions of the street areas of the semiconductor wafer substrate.

Claim 13

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, and a peripheral edge; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion Of the semiconductor wafer substrate, each semiconductor device having at least one bond pad formed thereon; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, the first coating comprising a glass coating; and a second coating covering the second side of the semiconductor wafer substrate.

Claim 14

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, and a peripheral edge; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion Of the semiconductor wafer substrate, each semiconductor device having at least one bond pad formed thereon; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, the first coating comprising a glass coating; and a second coating covering the second side of the semiconductor wafer substrate.

Claim 15

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, and a peripheral edge; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion of the semiconductor wafer substrate, each semiconductor device having at least one bond pad formed thereon; a first coating coveting the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate; and a second coating covering the second side of the semiconductor wafer substrate, the second coating comprising a glass coating.

Claim 16

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, and a peripheral edge; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion of the semiconductor wafer substrate, each semiconductor device having at least one bond pad formed thereon; a first coating coveting the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate; and a second coating covering the second side of the semiconductor wafer substrate, the second coating comprising a glass coating.

Claim 17

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, a peripheral edge, and a plurality of street areas thereon forming areas therebetween on the semiconductor wafer substrate, the semiconductor wafer substrate having portions thereof removed in the plurality of street areas thereof; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending over a portion of the semiconductor wafer substrate, each semiconductor device formed on the semiconductor wafer substrate being separated from an adjacent semiconductor device by the portions of the semiconductor wafer substrate removed from the street areas of the semiconductor wafer substrate, each semiconductor device having a plurality of peripheral edges formed by the portions of the semiconductor wafer substrate removed in the plurality of street areas and having at least one bond pad formed thereon; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate; and a second coating covering the second side of the semiconductor wafer substrate and substantially filling the portions of the street areas of the semiconductor wafer substrate which have been removed thereby separating areas of the semiconductor wafer substrate from other areas thereof.

Claim 18

A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, a peripheral edge, and a plurality of street areas thereon forming areas therebetween on the semiconductor wafer substrate, the semiconductor wafer substrate having portions thereof removed in the plurality of street areas thereof; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending over a portion of the semiconductor wafer substrate, each semiconductor device formed on the semiconductor wafer substrate being separated from an adjacent semiconductor device by the portions of the semiconductor wafer substrate removed from the street areas of the semiconductor wafer substrate, each semiconductor device having a plurality of peripheral edges formed by the portions of the semiconductor wafer substrate removed in the plurality of street areas and having at least one bond pad formed thereon; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate; and a second coating covering the second side of the semiconductor wafer substrate and substantially filling the portions of the street areas of the semiconductor wafer substrate which have been removed thereby separating areas of the semiconductor wafer substrate from other areas thereof.

Claim 19

The semiconductor wafer of claim 14, wherein the first coating further comprises: a coating on the first side of the semiconductor wafer substrate covering the plurality of semiconductor devices formed thereon except for the at least one bond pad formed on each semiconductor device.

Claim 20

The semiconductor wafer of claim 15, further comprising: a plurality of metal circuits located on the first coating on the first side of the semiconductor wafer substrate, at least one of the plurality of metal circuits being connected to the at least one bond pad of each semiconductor device.

Claim 21

The semiconductor wafer of claim 16, wherein the plurality of metal circuits further comprise: the at least one metal circuit connected to the at least one bond pad of each of the semiconductor devices engaging the bond pad to which it is connected and engaging the first coating on the first side of the semiconductor wafer substrate located around the at least one bond pad of each semiconductor device.

Claim 24

The method of claim 18, further comprising the step of: removing a portion of the first coating on the first side of the wafer substrate to uncover a portion of the at least one bond pad located on the at least one semiconductor device.

Claim 25

The method of claim 19, further comprising the step of: applying a third coating to the uncovered portion of the at least one bond pad of the at least one semiconductor device.

Claim 26

The method of claim 19, further comprising the step of: applying a third coating to the uncovered portion of the at least one bond pad of the at least one semiconductor device and a portion of the first coating adjacent the at least one bond pad of the semiconductor device.

Claim 29

The method of claim 22, wherein the step of removing a portion of the wafer substrate comprises: the portion of the wafer substrate removed from each side of the at least one semiconductor device substantially extending from the second side of the wafer substrate to substantially the first coating on the first side of the wafer substrate.

Claim 30

The method of claim 22, further comprising the step of: coating the second side of the wafer substrate with a second coating to substantially seal the second side of the wafer substrate.

Claim 31

The method of claim 24, further comprising the step of: separating the semiconductor device from the wafer substrate by removing a portion of the second coating substantially extending into the areas of the wafer substrate removed from each side of the semiconductor device.

Claim 32

The method of claim 22, further comprising the step of: coating the second side of the wafer substrate with a second coating to substantially seal the second side of the wafer substrate, the second coating substantially extending into the portions of the wafer substrate removed from the sides of the semiconductor device.

Claim 33

The method of claim 26, further comprising the step of: separating the semiconductor device from the wafer substrate by removing a portion of the second coating substantially extending into the areas of the wafer substrate removed from each side of the semiconductor device.

Claim 34

The method of claim 22, further comprising the step of: coating a portion of the at least one bond pad of the at least one semiconductor device with a third coating.

Claim 35

The method of claim 22, further comprising the step of: coating the uncovered portion of the at least one bond pad of the at least one semiconductor device and a portion of the first coating on the first side of the wafer substrate adjacent the bond pad with a third coating.

Claim 36

The method of claim 29, further comprising the step of: removing a portion of the third coating located adjacent the at least one bond pad of the at least one semiconductor device located on the wafer substrate.

Claim 37

The method of claim 22, further comprising the step of: separating the semiconductor device from the wafer substrate.

Claim 38

The method of claim 22, further comprising the step of: coating the second side of the wafer substrate with a second coating to substantially seal the second side of the wafer substrate, the second coating substantially extending into the portions of the wafer substrate removed from the sides of the semiconductor device and substantially adhering to the plurality of sides of the at least one semiconductor device formed on the wafer substrate.

Claim 39

The method of claim 32, further comprising the steps of: separating the semiconductor device from the wafer substrate by removing a portion of the second coating substantially extending into the areas of the wafer substrate removed from each side of the semiconductor device; and maintaining a portion of the second coating substantially adhering to the sides of the at least one semiconductor device located on the wafer substrate.

Claim 42

The method of claim 34, further comprising the step of: prior to coating the second side of the wafer substrate with a second coating the wafer substrate is thinned.

Claim 43

The method of claim 34, further comprising the step of: removing the second coating of resist from the second side of the wafer substrate.

Claim 44

The method of claim 34, wherein the third coating is a coating of glass.

Claim 45

The method of claim 34, further comprising the step of: applying a fourth coating of resist to the first side of the wafer substrate.

Claim 46

The method of claim 38, further comprising the step of: etching substantially the first coating on the first side of the wafer substrate in selected areas of the wafer substrate.

Claim 47

The method of claim 39, further comprising the step of: removing the fourth coating of resist on the first side of the wafer substrate after etching substantially the first coating on the first side of the wafer substrate in the selected areas of the wafer substrate.

Claim 48

The method of claim 40, further comprising the step of: applying a fifth coating to the first side of the wafer substrate.

Claim 49

The method of claim 41, wherein the fifth coating comprises a metal coating.

Claim 50

The method of claim 41, further comprising the step of: applying a sixth coating to the first side of the wafer substrate.

Claim 51

The method of claim 43, wherein the sixth coating is a resist.

Claim 52

The method of claim 43, further comprising the step of: etching portions of the fifth coating on the first side of the wafer substrate thereby leaving portions of the fifth coating on the first side of the wafer substrate in predetermined areas of the wafer substrate.

Claim 53

The method of claim 45, further comprising the step of: removing substantially the sixth coating from the first side of the wafer substrate thereby uncovering predetermined portions of the fifth coating on the first side of the wafer substrate.

Claim 54

The method of claim 46, further comprising the step of: dividing the wafer substrate into semiconductor devices.

Claim 55

The method of claim 46, wherein the step of dividing the wafer substrate comprises: sawing the wafer into semiconductor devices.