Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: (a) an array of memory cells in which respective data are stored and which are arranged in a matrix with rows and columns; (b) a row decoder which selects, based on a row address, a row of memory cells of said matrix; and (c) a column circuit which selects, based on a column address, a column of memory cells of said matrix; said column circuit comprising: detection current injection means for injecting, in a read mode of operation of reading data from a memory cell of said memory cell array selected by said row and column addresses, a data signal potential detection current into said selected memory cell, to detect a signal potential of said data stored in said selected memory cell.

Claim 3

A semiconductor integrated circuit device according to claim 1 wherein said detection current injection means is formed by a sense amplifier for injecting, in a read mode of operation of reading data from a selected memory cell of said memory cell array, an impedance detection current into said selected memory cell, to detect an impedance.

Claim 4

A semiconductor integrated circuit device according to claim 2 wherein said sense amplifier removes said impedance detection current injected into said selected memory cell after said data is read out of said selected memory cell.

Claim 5

A semiconductor integrated circuit device according to claim 2, wherein: (a) said sense amplifier is formed by establishing a flip-flop connection between a first inverter circuit and a second inverter circuit; said first inverter circuit comprising: a first transistor of a first transistor pair of a first conductivity type and a first transistor of a second transistor pair of a second conductivity type; said second inverter circuit comprising: a second transistor of said first transistor pair of the first conductivity type and a second transistor of said second transistor pair of the second conductivity type; (b) source electrodes of said first transistor pair of the first conductivity type which form a source electrode pair acts as a pair of input terminals for receiving said data from said selected memory cell; (c) a common contact point of source electrodes of said second transistor pair of the second conductivity type which form a source electrode pair is coupled to a power supply through a third transistor of the second conductivity type which is controlled by a given activation signal; (d) output terminals of said first and second inverter circuits which form an output terminal pair are connected, through a third and a fourth transistor of the first conductivity type, to said power supply; and (e) in said read mode, said third transistor of said second conductivity type is not activated simultaneously with said third and fourth transistors of the first conductivity type.

Claim 6

A semiconductor integrated circuit device according to claim 1, said memory cell array having a first and a second control line for controlling memory cells in said columns of said memory cell array; and said column circuit comprising: a bitline control circuit for applying, in a read mode of operation of reading data from a memory cell of said memory cells in said columns of said memory cell array, a first potential to said first control line and to said second control line, and for applying, in a write mode of operation of writing data into a memory cell of said memory cells in said columns of said memory cell array, either said first potential or a second potential to said first control line and applying a third potential to said second control line.

Claim 7

A semiconductor integrated circuit device according to claim 5 wherein said memory cell is formed by establishing a flip-flop connection among a first load transistor coupled to a first power supply, a second load transistor which forms a pair with said first load transistor, a first drive transistor coupled to a second power supply and a second drive transistor which forms a pair with said first drive transistor, said memory cell further including: (a) a first memory node which is coupled to said first load transistor and which holds a signal potential; (b) a second memory node which is coupled to said second load transistor and which holds a signal potential in complementary relationship with said signal potential held by said first memory node; (c) a first switch transistor which is serially coupled between said first memory node and said first control line and which is controlled by a third control line wherein one of source/drain electrodes of said first switch transistor is coupled to said first control line; and (d) a second switch transistor which is controlled by said second control line wherein one of source/drain electrodes of said second switch transistor is coupled to said first memory node and the other of said source/drain electrodes of said second switch transistor is coupled to the other of said source/drain electrodes of said first switch transistor; said second switch transistor being coupled serially between said first memory node and said first drive transistor.

Claim 8

A semiconductor integrated circuit device according to claim 6 wherein said second switch transistor is lower in threshold voltage than said first drive transistor, said second drive transistor and said first switch transistor.

Claim 9

A semiconductor integrated circuit device according to claim 6 wherein said second load transistor is smaller in size than said first load transistor and said second drive transistor.

Claim 10

A semiconductor integrated circuit device according to claim 6 wherein said memory cell is coupled, in parallel with said second drive transistor, between said second memory node and said second power supply and wherein said memory cell further includes a third switch transistor which is controlled by the potential at a contact point of said first switch transistor and said second switch transistor.

Claim 11

A semiconductor integrated circuit device according to claim 6 wherein said first power supply is voltage-reduced by means of a voltage reduction circuit.

Claim 12

A semiconductor integrated circuit device according to claim 10 wherein said voltage reduction circuit is a memory cell made up of transistors in conductivity-type opposition to corresponding transistors forming said memory cell of said memory cell array.

Claim 13

A semiconductor integrated circuit device according to claim 6 wherein the number of memory cells of said memory cell array coupled to said third control line is greater than the number of memory cells of said memory cell array coupled to said first and second control lines.

Claim 14

A semiconductor integrated circuit device according to claim 5 wherein said memory cell is formed by establishing a flip-flop connection among a first load transistor coupled to a first power supply, a second load transistor which forms a pair with said first load transistor, a first drive transistor coupled to a second power supply and a second drive transistor which forms a pair with said first drive transistor, said memory cell further including: (a) a first memory node which is coupled to said first load transistor and which holds a signal potential; (b) a second memory node which is coupled to said second load transistor and which holds a signal potential in complementary relationship with said signal potential held by said first memory node; (c) a first switch transistor which is serially coupled between said second memory node and said first control line and which is controlled by a third control line wherein one of source/drain electrodes of said first switch transistor is coupled to said first control line; (d) a second switch transistor which is controlled by said second control line wherein one of source/drain electrodes of said second switch transistor is coupled to said second memory node and the other of said source/drain electrodes of said second switch transistor is coupled to the other of said source/drain electrodes of said first switch transistor; and (e) a third switch transistor which is serially coupled between said first switch transistor and said second power supply and which is controlled by said first memory node.

Claim 15

A semiconductor integrated circuit device according to claim 13 wherein said first load transistor is smaller in size than said second load transistor.

Claim 16

A semiconductor integrated circuit device according to claim 13 wherein said memory cell is coupled, in parallel with said first drive transistor, between said first memory node and said second power supply and wherein said memory cell further includes a fourth switch transistor which is controlled by the potential at a contact point of said first switch transistor and said second switch transistor.

Claim 17

A semiconductor integrated circuit device according to claim 13 wherein said first power supply is voltage-reduced by means of a voltage reduction circuit.

Claim 18

A semiconductor integrated circuit device according to claim 16 wherein said voltage reduction circuit is a memory cell made up of transistors in conductivity-type opposition to corresponding transistors forming said memory cell of said memory cell array.

Claim 19

A semiconductor integrated circuit device according to claim 13 wherein the number of memory cells of said memory cell array coupled to said third control line is greater than the number of memory cells of said memory cell array coupled to said first and second control lines.