Semiconductor memory device having read/write circuitry

Claim 2

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of a MOS transistor and a capacitor; a bit line pair connected to said memory cells, said bit line pair consisting of first and second bit lines; a sense amplifier connected to said bit line pair for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pair; a first drive MOS transistor having a first terminal coupled to a first potential and a gate connected to one of said first and second bit lines, for extracting charges from one of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential and a gate connected to the other of said first and second bit lines, for extracting charges from the other of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; a first column selecting transistor having a first terminal connected to said one of said first and second data input/output lines, a second terminal connected to a second terminal of said first driver MOS transistor, and gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to a second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said other of said first and second bit lines, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate applied with a data write control signal for switching said first write transistor ON in a data writing operation; and a second write transistor having a first terminal connected to said one of said first and second bit lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal for switching said second write transistor ON in the data writing operation.

Claim 3

The memory device according to claim 1, wherein said sense amplifier for amplifying a potential difference is a CMOS sense amplifier including a first flip-flop consisting of two n-channel MOS transistors and a second flip-flop consisting of two p-channel MOS transistors, said first and second driver MOS transistors are n-channel MOS transistors, said first and second column selecting transistors are n-channel MOS transistors, and said first and second write transistors are n-channel MOS transistors.

Claim 4

The memory device according to claim 1, wherein said sense amplifier for amplifying a potential difference is a CMOS sense amplifier including a first flip-flop consisting of two n-channel MOS transistors and a second flip-flop consisting of two p-channel MOS transistors, said first and second driver MOS transistors are p-channel transistors, said first and second column selecting transistors are p-channel MOS transistors, and said first and second write transistors are p-channel MOS transistors.

Claim 5

The memory device according to claim 1, further comprising: a first load MOS transistor having a first terminal connected to said second terminal of said first driver MOS transistor, a second terminal connected to a second potential, and a gate connected to said one of said first and second bit lines; and a second load MOS transistor having a first terminal connected to said second terminal of said second driver MOS transistor, a second terminal connected to said second potential, and a gate connected to said one of said first and second bit lines, wherein said first and second load MOS transistors constitute a current mirror load.

Claim 6

The memory device according to claim 1, further comprising: a current suppression MOS transistor having a first terminal connected to said first terminals of said first and second driver MOS transistors and a second terminal connected to said first potential.

Claim 7

The memory device according to claim 1, wherein said first potential is a ground potential.

Claim 8

The memory device according to claim 1, wherein said first potential is a power source potential V CC .

Claim 9

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of MOS transistor and a capacitor; a bit line pair connected to said memory cells, said bit line pair consisting of first and second bit lines; a sense amplifier connected to said bit line pair, for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pair; a first driver MOS transistor having a first terminal coupled to a first potential and a gate connected to one of said first and second bit lines, for extracting charges from one of said input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential and a gate connected to the other of said first and second bit lines, for extracting charges from the other of said input/output lines in the data reading operation, and for amplifying data input/output line signals; a first load MOS transistor having a first terminal connected to a second terminal of said first driver MOS transistor, a second terminal connected to a second potential, and a gate connected to said gate of said first driver MOS transistor, whereby said first driver MOS transistor and said first load MOS transistor constitute a first CMOS inverter; a second load MOS transistor having a first terminal connected to a second terminal of said second driver MOS transistor, a second terminal connected to said second potential, and a gate connected to said gate of said second driver MOS transistor, whereby said second driver MOS transistor and said second load MOS transistor constitute a second CMOS inverter; a first column selecting transistor having a first terminal connected to said one of said first and second data input/output lines; a second terminal connected to said second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said other of said first and second bit lines, a second terminal connected to said second terminal of said first driver MOS transistor and a gate applied with a data write control signal for switching said first write transistor ON in a data writing operation; and a second write transistor having a first terminal connected to said one of said first and second bit lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal for switching said second write transistor ON in the data writing operation.

Claim 10

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of MOS transistor and a capacitor; a bit line pair connected to said memory cells, said bit line pair consisting of first and second bit lines; a sense amplifier connected to said bit line pair, for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pair; a first driver MOS transistor having a first terminal coupled to a first potential and a gate connected to one of said first and second bit lines, for extracting charges from one of said input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential and a gate connected to the other of said first and second bit lines, for extracting charges from the other of said input/output lines in the data reading operation, and for amplifying data input/output line signals; a first load MOS transistor having a first terminal connected to a second terminal of said first driver MOS transistor, a second terminal connected to a second potential, and a gate connected to said gate of said first driver MOS transistor, whereby said first driver MOS transistor and said first load MOS transistor constitute a first CMOS inverter; a second load MOS transistor having a first terminal connected to a second terminal of said second driver MOS transistor, a second terminal connected to said second potential, and a gate connected to said gate of said second driver MOS transistor, whereby said second driver MOS transistor and said second load MOS transistor constitute a second CMOS inverter; a first column selecting transistor having a first terminal connected to said one of said first and second data input/output lines; a second terminal connected to said second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said other of said first and second bit lines, a second terminal connected to said second terminal of said first driver MOS transistor and a gate applied with a data write control signal for switching said first write transistor ON in a data writing operation; and a second write transistor having a first terminal connected to said one of said first and second bit lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal for switching said second write transistor ON in the data writing operation.

Claim 11

The memory device according to claim 8, further comprising: a current suppression MOS transistor having a first terminal connected to said first terminals of said first and second driver MOS transistors and a second terminal connected to said first potential.

Claim 12

The memory device according to claim 8, further comprising: a current suppression MOS transistor having a first terminal connected to said first terminals of said first and second driver MOS transistors, a second terminal connected to said first potential, and a gate connected to said column selection line.

Claim 13

The memory device according to claim 8, wherein said first potential is a ground potential.

Claim 14

The memory device according to claim 8, wherein said first potential is a power source potential Vcc.

Claim 15

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of a MOS transistor and a capacitor; bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines; sense amplifiers each connected to one of said bit line pairs for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pairs; a first driver MOS transistor having a first terminal coupled to a first potential, for extracting charges from one of said first and second input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential, for extracting charges from the other of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; bit line pair selecting means, connected to gates of said first and second driver MOS transistors, for selecting one bit line pair from said plurality of bit line pairs in accordance with an address; a first column selecting transistor having a first terminal connected to said one of said first and second data input/output lines, a second terminal connected to a second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to a second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate supplied with a data write control signal for switching said first write transistor ON in a data writing operation; and a second write transistor having a fist terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal for switching said second write transistor ON in the data writing operation; wherein said bit line pair selecting means has first and second output lines and wherein said gate of said first driver MOS transistor is connected to said second output line and said gate of said second driver MOS transistor is connected to said first output line, and said first terminal of said first write transistor is connected to said first output line and said first terminal of said second write transistor is connected to said second output line.

Claim 16

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of a MOS transistor and a capacitor; bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines; sense amplifiers each connected to one of said bit line pairs for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pairs; a first driver MOS transistor having a first terminal coupled to a first potential, for extracting charges from one of said first and second input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential, for extracting charges from the other of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; bit line pair selecting means, connected to gates of said first and second driver MOS transistors, for selecting one bit line pair from said plurality of bit line pairs in accordance with an address; a first column selecting transistor having a first terminal connected to said one of said first and second data input/output lines, a second terminal connected to a second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to a second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate supplied with a data write control signal for switching said first write transistor ON in a data writing operation; and a second write transistor having a fist terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal for switching said second write transistor ON in the data writing operation; wherein said bit line pair selecting means has first and second output lines and wherein said gate of said first driver MOS transistor is connected to said second output line and said gate of said second driver MOS transistor is connected to said first output line, and said first terminal of said first write transistor is connected to said first output line and said first terminal of said second write transistor is connected to said second output line.

Claim 17

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of a MOS transistor and a capacitor; bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines; sense amplifiers each connected to one of said bit line pairs for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pairs; a first driver MOS transistor having a first terminal coupled to a first potential, for extracting charges from one of said first and second input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential, for extracting charges from the other of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; a first load MOS transistor having a first terminal connected to a second terminal of said first driver MOS transistor, a second terminal connected to a second potential, and a gate connected to a gate of said first driver MOS transistor, whereby said first driver MOS transistor and said first load MOS transistor constitute a first CMOS inverter; a second load MOS transistor having a first terminal connected to a second terminal of and second driver MOS transistor, a second terminal connected to said second potential, and a gate connected to a gate of said second driver MOS transistor, whereby said second driver MOS transistor and said second load MOS transistor constitute a second CMOS inverter; bit line pair selecting means, connected to said gates of said first and second driver MOS transistors, for selecting one bit line pair from said plurality of bit line pairs in accordance with an address; a first column selecting transistor having a first terminal connected to one of said first and second data input/output lines, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate supplied with a data write control signal to switch said first write transistor ON in a data writing operation; and a second write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal to switch said second write transistor ON in the data writing operation; wherein said bit line pair selecting means has first and second output lines and wherein said gate of said first driver MOS transistor is connected to said second output line and said gate of said second driver MOS transistor is connected to said first output line, and said first terminal of said first write transistor is connected to said first output line and said first terminal of said second write transistor is connected to said second output line.

Claim 18

A dynamic type semiconductor memory device, comprising: a plurality of memory cells each consisting of a MOS transistor and a capacitor; bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines; sense amplifiers each connected to one of said bit line pairs for amplifying a potential difference between said first and second bit lines; a data input/output line pair consisting of first and second data input/output lines for inputting data to and outputting data from said bit line pairs; a first driver MOS transistor having a first terminal coupled to a first potential, for extracting charges from one of said first and second input/output lines in a data reading operation, and for amplifying data input/output line signals; a second driver MOS transistor having a first terminal coupled to said first potential, for extracting charges from the other of said first and second input/output lines in the data reading operation, and for amplifying data input/output line signals; a first load MOS transistor having a first terminal connected to a second terminal of said first driver MOS transistor, a second terminal connected to a second potential, and a gate connected to a gate of said first driver MOS transistor, whereby said first driver MOS transistor and said first load MOS transistor constitute a first CMOS inverter; a second load MOS transistor having a first terminal connected to a second terminal of and second driver MOS transistor, a second terminal connected to said second potential, and a gate connected to a gate of said second driver MOS transistor, whereby said second driver MOS transistor and said second load MOS transistor constitute a second CMOS inverter; bit line pair selecting means, connected to said gates of said first and second driver MOS transistors, for selecting one bit line pair from said plurality of bit line pairs in accordance with an address; a first column selecting transistor having a first terminal connected to one of said first and second data input/output lines, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate connected to a column selection line; a second column selecting transistor having a first terminal connected to said other of said first and second data input/output lines, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate connected to said column selection line; a first write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said first driver MOS transistor, and a gate supplied with a data write control signal to switch said first write transistor ON in a data writing operation; and a second write transistor having a first terminal connected to said bit line pair selecting means, a second terminal connected to said second terminal of said second driver MOS transistor, and a gate applied with the data write control signal to switch said second write transistor ON in the data writing operation; wherein said bit line pair selecting means has first and second output lines and wherein said gate of said first driver MOS transistor is connected to said second output line and said gate of said second driver MOS transistor is connected to said first output line, and said first terminal of said first write transistor is connected to said first output line and said first terminal of said second write transistor is connected to said second output line.