Patent US5680342A successfully refreshed from Google Patents.
US5680342A
Expired / Lapsed
US
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Memory module package with address bus buffering
Assignee: International Business Machines Corp
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Filing: 1996-04-10
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Granted: 1997-10-21
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Expires: 2016-04-10
Abstract
Abstract Systems and methods for connecting multiple memory modules to a computer system while controlling address bus and data bus loading and termination effects. In one form, the modules are connected to a printed circuit board carrying the address and data buses using dendrite enhanced bonds between module contacts and printed circuit board pads. The address bus loading which typically characterizes the addition of memory to a computer system is minimized through the inclusion of an address buffer module with each group of memory modules in a module expansion carrier. Data bus termination characteristics are controlled using jumpers within the modules. The invention is particularly suited for use with modules configured with chip edge interconnect technology, allowing the computer system user to expand the system memory without unduly effecting the address bus and data bus line characteristics.
Inventors
- 👤 Richard Francis Frankeny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:32
CPC Classifications
G; G11; G11C; G11C5/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
115 words
In a processor memory array having multiple modules, a multiple line data bus, and a multiple line address bus, an address signal buffer system, comprising: means for distributing address signals over address lines common to a first set of multiple memory modules; means for distributing address signals to address lines common to a second set of multiple memory modules; a buffer module connected to receive address signals from the address lines common to the first set of multiple memory modules and distribute buffered address signals to the address lines common to the second set of multiple memory modules; and means for mounting the buffer module and multiple memory modules in a common memory array carrier.
Claim 2
Dependent Claim
115 words
In a processor memory array having multiple modules, a multiple line data bus, and a multiple line address bus, an address signal buffer system, comprising: means for distributing address signals over address lines common to a first set of multiple memory modules; means for distributing address signals to address lines common to a second set of multiple memory modules; a buffer module connected to receive address signals from the address lines common to the first set of multiple memory modules and distribute buffered address signals to the address lines common to the second set of multiple memory modules; and means for mounting the buffer module and multiple memory modules in a common memory array carrier.
Claim 3
Dependent Claim
37 words
The apparatus recited in claim 1, wherein the address lines common to the first and second sets of multiple memory modules are wiring patterns on a printed circuit board onto which the memory array carrier is mounted.
Claim 4
Dependent Claim
44 words
The apparatus recited in claim 1, wherein the connection between the buffer modules and the address lines common to the first and second sets of multiple modules is through dendrites formed on at least one of a pair of surfaces mated for each connection.
Claim 5
Dependent Claim
44 words
The apparatus recited in claim 2, wherein the connection between the buffer modules and the address lines common to the first and second sets of multiple modules is through dendrites formed on at least one of a pair of surfaces mated for each connection.
Claim 6
Dependent Claim
36 words
The apparatus recited in claim 3, wherein contacts on the buffer module used to receive and distribute address signals are aligned with address line patterns defined by the first and second sets of multiple memory modules.
Claim 7
Dependent Claim
36 words
The apparatus recited in claim 4, wherein contacts on the buffer module used to receive and distribute address signals are aligned with address line patterns defined by the first and second sets of multiple memory modules.
Claim 8
Dependent Claim
24 words
The apparatus recited in claim 5, wherein the address signals distributed over the address lines include at least one line providing RAS/CAS strobe signals.
Claim 9
Dependent Claim
24 words
The apparatus recited in claim 6, wherein the address signals distributed over the address lines include at least one line providing RAS/CAS strobe signals.
Claim 10
Dependent Claim
33 words
The apparatus recited in claim 7, further comprising: means in the modules for connecting in segments of the data bus lines to extend the data bus with an addition of a memory module.
Claim 11
Dependent Claim
32 words
The apparatus recited in claim 8, further comprising: means in the modules for connecting segments of the data bus to extend the data bus lines with addition of a memory array carrier.
Claim 12
Independent Claim
166 words
A method of interconnecting a processor memory array to provide buffered address signals to memory modules of the array, comprising the steps of: forming on a printed circuit board address lines in a pattern having first and second segments, with a conductive break between the segments; attaching a first set of memory modules to the board so that address lines of the first set of memory modules are connected to respective address lines in the first segment of the pattern; attaching a second set of memory modules to the board so that address lines of the second set of memory modules are connected to respective address lines in the second segment of the pattern; and attaching an address buffer module to the board so that input lines of the address buffer module are connected to respective address lines in the first segment of the pattern and output lines of the address buffer module are connected to respective address lines in the second segment of the pattern.
Claim 13
Independent Claim
166 words
A method of interconnecting a processor memory array to provide buffered address signals to memory modules of the array, comprising the steps of: forming on a printed circuit board address lines in a pattern having first and second segments, with a conductive break between the segments; attaching a first set of memory modules to the board so that address lines of the first set of memory modules are connected to respective address lines in the first segment of the pattern; attaching a second set of memory modules to the board so that address lines of the second set of memory modules are connected to respective address lines in the second segment of the pattern; and attaching an address buffer module to the board so that input lines of the address buffer module are connected to respective address lines in the first segment of the pattern and output lines of the address buffer module are connected to respective address lines in the second segment of the pattern.
Claim 14
Dependent Claim
42 words
The method recited in claim 11, wherein the connection between the modules and address lines of the pattern is made but by physical contact involving the use of dendrites formed on at least one of a pair of surfaces mated for connection.
Claim 15
Dependent Claim
19 words
The method recited in claim 12, wherein the first and second segments of the address line pattern are aligned.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |