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US5678028A
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Hardware-software debugger using simulation speed enhancing techniques including skipping unnecessary bus cycles, avoiding instruction fetch simulation, eliminating the need for explicit clock pulse generation and caching results of instruction decoding
Assignee: Mitsubishi Electric Research Laboratories Inc
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Filing: 1994-10-25
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Granted: 1997-10-14
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Expires: 2014-10-25
Abstract
Abstract The speed of a hardware-software debugger is markedly increased through the use of high speed simulators which ignore all systems operations except those where design errors are expected to manifest themselves, by skipping CPU bus cycles of no interest for the simulation, by not explicitly simulating periodic clock signals and generating only schedules of clock signals, and by caching instructions when alien computers are used in the simulation process to eliminate decoding of the instructions of the target computer.
Inventors
- 👤 Mikhail Bershteyn
- 👤 Ross Thomas Casley
- 👤 Chiahon Chien
- 👤 Abhijit Ghosh
- 👤 Anurag Jain
- 👤 Michael Leigh Lipsie
- 👤 Donald Tarrodaychik
- 👤 Osamu Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/3698; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
205 words
A system for increasing the speed of a hardware-software debugger for debugging a target system having a CPU, a memory, and a number of hardware modules, a interconnected with a bus, comprising: means for simulating said target system including a CPU simulator, a memory simulator, a number of simulators for said hardware modules, and a simulation manager coupled to said CPU simulator, said memory simulator and said number of simulators for said hardware modules for executing simulation control and debugging commands periodically calling different simulators and passing control to the appropriate simulator; a bus simulator for interconnecting said hardware module simulators, said memory simulator and said CPU simulator, said bus providing signals corresponding to bus cycles; and means for skipping bus cycles not necessary for simulation wherein said skipping means includes means for determining whether there is an instruction fetch on said bus, or a data access cycle on said bus, and if there is a data access cycle, determining whether bus operation for said data access cycle is for said memory rather than one of said hardware modules, whereby it is not necessary to interpret every bus signal by avoiding instruction fetch simulation and whereby the speed increase is due to skipping unnecessary cycles.
Claim 2
Independent Claim
205 words
A system for increasing the speed of a hardware-software debugger for debugging a target system having a CPU, a memory, and a number of hardware modules, a interconnected with a bus, comprising: means for simulating said target system including a CPU simulator, a memory simulator, a number of simulators for said hardware modules, and a simulation manager coupled to said CPU simulator, said memory simulator and said number of simulators for said hardware modules for executing simulation control and debugging commands periodically calling different simulators and passing control to the appropriate simulator; a bus simulator for interconnecting said hardware module simulators, said memory simulator and said CPU simulator, said bus providing signals corresponding to bus cycles; and means for skipping bus cycles not necessary for simulation wherein said skipping means includes means for determining whether there is an instruction fetch on said bus, or a data access cycle on said bus, and if there is a data access cycle, determining whether bus operation for said data access cycle is for said memory rather than one of said hardware modules, whereby it is not necessary to interpret every bus signal by avoiding instruction fetch simulation and whereby the speed increase is due to skipping unnecessary cycles.
Claim 3
Dependent Claim
66 words
The system of claim 1 and further including a clock source simulator for generating schedules of periodic clock signals at initialization times to provide repetitive simulation of said periodic clock signals, and means coupled to said bus for decoding said schedule and for producing a local set of clock pulses at the time determined by said schedule, whereby all clock pulses need not be explicitly generated.
Claim 4
Dependent Claim
80 words
The system of claim 1 wherein the program running on said CPU involves repetitive execution of the same instruction, and further including a cache for temporary storage of decoded instructions and for retrieval thereof by translation, such that after a first decoding is done, the next time said same instruction is encountered only the results of the translation of said some instruction are retrieved from said cache, thus to take advantage of the caching of the results of instruction decoding.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |