Patent US5677210A successfully refreshed from Google Patents.
US5677210A
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Method of producing a fully planarized concave transistor
Assignee: SK Hynix Inc
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Filing: 1996-11-22
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Granted: 1997-10-14
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Expires: 2016-11-22
Abstract
Abstract A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.
Inventors
- 👤 Chan Kwang Park
- 👤 Yo Hwan Koh
- 👤 Seong Min Hwang
- 👤 Kwang Myoung Roh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/608; H10D30/022; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10D64/025; H10D64/027; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/163; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A method of producing a fully planar concave transistor, comprising the steps of: forming a lightly doped layer having a first dopant concentration on a semiconductor substrate; forming a highly doped layer having a second dopant concentration higher than the first dopant concentration on the lightly doped layer; selectively etching the highly doped layer and the lightly doped layer to expose a part of the semiconductor substrate between opposite sidewalls of the lightly doped layer and the highly doped Layer and to form patterns for a source and a drain; forming a thick insulating layer on a surface and the opposite sidewalls of the highly doped layer so that the highly doped layer forms the source and the drain from the patterns thereof; then, forming a gate insulating layer on the thick insulating layer, the opposite sidewalls of the lightly doped layer, and the exposed part of the semiconductor substrate; then, forming a gate electrode between the opposite sidewalls of the lightly doped layer and the highly doped layer between the source and the drain and; etching the gate electrode to make the gate electrode planar with the gate insulating layer on the thick insulating layer.
Claim 2
Independent Claim
196 words
A method of producing a fully planar concave transistor, comprising the steps of: forming a lightly doped layer having a first dopant concentration on a semiconductor substrate; forming a highly doped layer having a second dopant concentration higher than the first dopant concentration on the lightly doped layer; selectively etching the highly doped layer and the lightly doped layer to expose a part of the semiconductor substrate between opposite sidewalls of the lightly doped layer and the highly doped Layer and to form patterns for a source and a drain; forming a thick insulating layer on a surface and the opposite sidewalls of the highly doped layer so that the highly doped layer forms the source and the drain from the patterns thereof; then, forming a gate insulating layer on the thick insulating layer, the opposite sidewalls of the lightly doped layer, and the exposed part of the semiconductor substrate; then, forming a gate electrode between the opposite sidewalls of the lightly doped layer and the highly doped layer between the source and the drain and; etching the gate electrode to make the gate electrode planar with the gate insulating layer on the thick insulating layer.
Claim 3
Dependent Claim
21 words
A method according to claim 1, wherein the step of forming said thick insulating layer comprises a low temperature oxidation step.
Claim 4
Dependent Claim
22 words
A method according to claim 2, wherein said low temperature oxidation step is performed in a temperature of 750 to 950 C.
Claim 5
Dependent Claim
131 words
A method according to claim 1, wherein the step of forming a thick insulating layer on the surface and the sidewall of the highly doped layer comprises the steps of: forming an insulating layer on the opposite sidewalls of the highly doped layer and the lightly doped layer such that the insulating layer on the sidewalls of the highly doped layer is thicker than the insulating layer formed on the sidewalls of the lightly doped layer; and blanket etching the insulating layer to remove the insulating layer formed on the sidewalls of the lightly doped layer to expose first and second lightly doped layers while leaving a thick insulating layer formed on the sidewalls of the highly doped layer so that the highly doped layer forms the source and the drain.
Claim 6
Dependent Claim
63 words
A method according to claim 1, wherein forming a thick insulating layer on a surface and a sidewall of the highly doped layer includes forming a thickness of the insulating layer formed on a side of the highly doped layer to be two to ten times thicker than a thickness of the insulating layer formed on a side of the lightly doped layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |