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US5677206A
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Method of making a poly-silicon thin film transistor having lightly doped drain structure
Assignee: Samsung Display Co Ltd
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Filing: 1996-02-26
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Granted: 1997-10-14
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Expires: 2016-02-26
Abstract
Abstract A poly-silicon thin film transistor having LDD structure which has very low source/drain resistance is described. A TFT according to a preferred embodiment of the present invention, has, on a substrate, an active poly-silicon layer with a heavily-doped region on an outer peripheral thereof, a lightly doped region on ban inside the outer peripheral band and an un-doped region on a center part thereof. A gate insulating layer is comprised of a lower oxide layer, a nitride layer and an upper oxide layer. The lower oxide layer is formed over the whole active poly-silicon layer, but the nitride layer and the upper oxide layer are formed only on the un-doped portions of the active poly-silicon layer. A gate electrode is then formed on the upper oxide layer. A method for forming this structure is also described, which method uses a dry etch to remove the upper oxide layer and the nitride layer, but not the lower oxide layer prior to ion implantation of the active region.
Inventors
- 👤 Joo-hyung Lee
- 👤 Suk-Bum Mah
- 👤 Jin-hong Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:38
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
195 words
A method of manufacturing a poly-silicon thin film transistor comprising the steps of: depositing an active poly-silicon layer on a substrate; depositing a lower oxide layer over said active poly-silicon layer; depositing a nitride layer over said lower oxide layer; depositing an upper oxide layer over said nitride layer; forming a gate electrode over said upper oxide layer; removing portions of said upper oxide layer and said nitride layer by photolithography using said gate electrode as a mask to expose portions of said lower oxide layer; forming a lightly doped region by implanting ions at a lower-dose in said active poly-silicon layer through the exposed portion of the lower oxide layer using said gate electrode as a first mask; forming a poly-spacer pattern by depositing a poly-spacer and then patterning said poly-spacer pattern so that a poly-spacer is located over a portion of said lower oxide layer adjacent said gate electrode; implanting ions at a high-dose in said active poly-silicon layer through said lower oxide layer using said gate electrode and poly-spacer as a second mask to form a heavily doped region in an outer peripheral portion of said active poly-silicon; and removing the poly-spacer.
Claim 2
Independent Claim
195 words
A method of manufacturing a poly-silicon thin film transistor comprising the steps of: depositing an active poly-silicon layer on a substrate; depositing a lower oxide layer over said active poly-silicon layer; depositing a nitride layer over said lower oxide layer; depositing an upper oxide layer over said nitride layer; forming a gate electrode over said upper oxide layer; removing portions of said upper oxide layer and said nitride layer by photolithography using said gate electrode as a mask to expose portions of said lower oxide layer; forming a lightly doped region by implanting ions at a lower-dose in said active poly-silicon layer through the exposed portion of the lower oxide layer using said gate electrode as a first mask; forming a poly-spacer pattern by depositing a poly-spacer and then patterning said poly-spacer pattern so that a poly-spacer is located over a portion of said lower oxide layer adjacent said gate electrode; implanting ions at a high-dose in said active poly-silicon layer through said lower oxide layer using said gate electrode and poly-spacer as a second mask to form a heavily doped region in an outer peripheral portion of said active poly-silicon; and removing the poly-spacer.
Claim 3
Dependent Claim
30 words
The method of manufacturing a poly-silicon thin film transistor of claim 1, further comprising the step of forming a top oxide layer over said gate electrode before forming said poly-spacer.
Claim 4
Dependent Claim
26 words
The method of manufacturing a poly-silicon thin film transistor of claim 1, wherein said step of forming said gate electrode forms said gate electrode of poly-silicon.
Claim 5
Dependent Claim
20 words
The method of manufacturing a poly-silicon thin film transistor of claim 1 wherein said removing step uses a dry etch.
Claim 6
Dependent Claim
35 words
The method of manufacturing a poly-silicon thin film transistor of claim 4, wherein a selectivity ratio of etching between said upper oxide layer and said nitride layer is less than 1:2 during said removing step.
Claim 7
Dependent Claim
24 words
The method of manufacturing a poly-silicon thin film transistor of claim 1, wherein said step of forming said poly-spacer forms said poly-spacer of poly-silicon.
Claim 8
Dependent Claim
25 words
The method of manufacturing a poly-silicon thin film transistor of claim 6, wherein a thickness of said poly-spacer is in the range of 1000-4000 Å.
Claim 9
Dependent Claim
32 words
The method of manufacturing a poly-silicon thin film transistor of claim 1, wherein said steps of depositing said lower oxide layer and depositing said upper oxide layer are performed using thermal oxidation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |