US5675501A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of designing semiconductor integrated circuit apparatus having no dead space
Assignee: Toshiba Corp
•
Filing: 1995-03-15
•
Granted: 1997-10-07
•
Expires: 2015-03-15
Abstract
Abstract A method of designing a semiconductor integrated circuit apparatus vice comprises: a placement step of generating row information indicating a transistor row in which transistors required for the configuration of a transistor row to be designed are placed so that wiring length is as short as possible on the basis of net connection information of transistors, size information of various transistors constituting the net, and ideal module size information which provides constraint relating to sizes in X-direction and sizes in Y-direction perpendicular to the X-direction of the transistor row in which the various transistors are arranged in the X-direction; a row size determination step of generating, on the basis of the row information, row size information indicating sizes in the X-direction and the Y-direction of the transistor row that the row information indicates; and a parallel arrangement step of carrying out parallel arrangement of transistors constituting the transistor row so that the transistor row that the row information indicates falls within sizes in X-direction and Y-direction that the row size information indicates.
Inventors
- 👤 Sachiko Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:21
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
192 words
A method of designing a semiconductor integrated circuit apparatus comprising: a placement step of generating row information indicating a transistor row in which transistors required for the configuration of a transistor row to be designed so that wiring length is as short as possible, on the basis of net description information of transistors, size information of various transistors constituting net, and ideal module size information which provides constraint relating to size in the X-direction and in Y-direction perpendicular to the X-direction of the transistor row in which the various transistors are placed in the X-direction; a row size determination step of generating row size information indicating sizes in the X-direction and Y-direction of the transistor rows; each row size determination step of generating, on the basis of the row sizes information, row size indicating size in the X-direction and sizes in the Y-direction of the transistor rows that the rows information indicates; and a parallel arrangement step of carrying out parallel arrangement of transistors constituting the transistor row so that the transistor row that the row information indicates falls within sizes in the X-direction and Y-direction that the row size information indicates.
Claim 2
Independent Claim
192 words
A method of designing a semiconductor integrated circuit apparatus comprising: a placement step of generating row information indicating a transistor row in which transistors required for the configuration of a transistor row to be designed so that wiring length is as short as possible, on the basis of net description information of transistors, size information of various transistors constituting net, and ideal module size information which provides constraint relating to size in the X-direction and in Y-direction perpendicular to the X-direction of the transistor row in which the various transistors are placed in the X-direction; a row size determination step of generating row size information indicating sizes in the X-direction and Y-direction of the transistor rows; each row size determination step of generating, on the basis of the row sizes information, row size indicating size in the X-direction and sizes in the Y-direction of the transistor rows that the rows information indicates; and a parallel arrangement step of carrying out parallel arrangement of transistors constituting the transistor row so that the transistor row that the row information indicates falls within sizes in the X-direction and Y-direction that the row size information indicates.
Claim 3
Dependent Claim
61 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 1, wherein the method includes, before the placement step or after the row size determination step, a step of carrying out grouping of p·n pair of transistors constituting a module to be designed in accordance with a specific condition on the basis of ideal module size information.
Claim 4
Dependent Claim
41 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 1, wherein in said placement step of generating said row information, an arrangement is performed with a width smaller than an X-direction size of a module size.
Claim 5
Dependent Claim
49 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 3, wherein the method further includes a row size determination step of determining sizes in Y-direction with respect to entire transistor rows in the manner of matching a size in X-direction of an ideal module.
Claim 6
Dependent Claim
65 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 3, wherein the method further includes a row size determination step of determining sizes in Y-direction with respect to entire transistor rows in the manner of matching a size in X-direction of an ideal module, when the longest transistor row coincides with a size in X-direction of an ideal module size.
Claim 7
Dependent Claim
37 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 1, wherein in said placement step of generating said row information, a placement is performed by attaching importance to a connection of nets.
Claim 8
Dependent Claim
64 words
A method of designing a semiconductor integrated circuit apparatus as set forth in claim 1, wherein the method further includes a row size determination step of determining, when a size in Y-direction of an ideal module size is defined, a predetermined size or total size of respective transistor row in Y-direction in the manner of coinciding with a size of an ideal module size.
Claim 9
Dependent Claim
47 words
A semiconductor integrated circuit apparatus designed by the designing method according to claim 1; said apparatus is designed in the manner that all the transistor is stored within a scope of a module width which is determined without breaking a placement relationship determined in said placement step.
References Cited (Backward Citations)
US4695978A
Cited
US4910680A
Cited
US5416720A
Cited
US5401988A
Cited
US5212653A
Cited
US5392233A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |