Standard cell layout arrangement for an LSI circuit

Claim 2

A standard cell comprising: first and second voltage lines of a first voltage level extending parallel to each other; a third voltage line of a second voltage level different from said first voltage level, said third voltage line extending between said first and second voltage lines parallel to said first and second voltage lines; and a circuit arrangement formed in areas interposed between said third voltage line and said first voltage line and between said third voltage line and said second voltage line.

Claim 3

A cell, comprising: at least three power source wires arranged at predetermined intervals, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; and at least two circuit-element arranging areas respectively interposed between each adjacent pair of said power source wires such that a lateral length of said cell is minimized, said at least two circuit-element arranging areas completely containing circuit elements which form a standard cell.

Claim 4

A cell, comprising: at least three power source wires arranged at predetermined intervals, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; and at least two circuit-element arranging areas respectively interposed between each adjacent pair of said power source wires such that a lateral length of said cell is minimized, said at least two circuit-element arranging areas completely containing circuit elements which form a standard cell.

Claim 5

The cell as claimed in claim 2, wherein one of said power source wires is a low potential power source wire and the other power source wires are high potential power source wires.

Claim 6

The cell as claimed in claim 2, wherein electric potentials of said at least three power source wires are arranged symmetrically from a central position of said power source wires toward positions away from said central position.

Claim 7

An electrical circuit comprising: a plurality of standard cells each including at least three power source wires arranged at predetermined intervals and at least two circuit-element arranging areas respectively interposed between each adjacent pair of said power source wires such that a lateral length of said standard cells is minimized, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; wherein said standard cells are arranged so as to make an input terminal and an output terminal, of adjacent standard cells, next to each other away from a centerline of said standard cells.

Claim 8

An electrical circuit comprising: a plurality of standard cells each including at least three power source wires arranged at predetermined intervals and at least two circuit-element arranging areas respectively interposed between each adjacent pair of said power source wires such that a lateral length of said standard cells is minimized, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; wherein said standard cells are arranged so as to make an input terminal and an output terminal, of adjacent standard cells, next to each other away from a centerline of said standard cells.

Claim 9

An arrangement of at least two standard cells, said arrangement comprising: a first standard cell having at least three power source wires, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; a second standard cell having at least two power source wires; and a connecting cell for connecting said first and second standard cells to each other.

Claim 10

An arrangement of at least two standard cells, said arrangement comprising: a first standard cell having at least three power source wires, two of said three power source wires providing power at a first voltage level and a third of said three power source wires providing power at a second voltage level which is different from said first voltage level; a second standard cell having at least two power source wires; and a connecting cell for connecting said first and second standard cells to each other.

Claim 11

The arrangement as claimed in claim 6, wherein the first standard cells each having at least three power source wires are assembled together to form a cell group, the second standard cells each having at least two power source wires are assembled together to form another cell group, and wherein said two cell groups are connected to each other with one connecting cell.

Claim 12

A row of standard cells each provided with a high voltage source line and a low voltage line which are coupled to corresponding lines of adjacent cells to form continuous lines, wherein: at least one of said standard cells is provided with a third voltage source line which is electrically connected to one of said high voltage source line and said low voltage source line.

Claim 13

A row of standard cells each provided with a high voltage source line and a low voltage line which are coupled to corresponding lines of adjacent cells to form continuous lines, wherein: at least one of said standard cells is provided with a third voltage source line which is electrically connected to one of said high voltage source line and said low voltage source line.

Claim 14

A standard cell for use in a large scale integrated circuit which includes a binary logic circuit, said standard cell comprising: constituent semiconductor elements; and three voltage source lines located in the same level layer and extending parallel to each other through said standard cell and providing binary logic levels for said semiconductor elements, two of said three voltage source lines providing power at a first voltage level and a third voltage source line of said three voltage source lines providing power at a second voltage level which is different from said first voltage level.

Claim 15

A standard cell for use in a large scale integrated circuit which includes a binary logic circuit, said standard cell comprising: constituent semiconductor elements; and three voltage source lines located in the same level layer and extending parallel to each other through said standard cell and providing binary logic levels for said semiconductor elements, two of said three voltage source lines providing power at a first voltage level and a third voltage source line of said three voltage source lines providing power at a second voltage level which is different from said first voltage level.

Claim 16

A row of standard cells operative with first and second voltages, which are different from each other, as a power supply, each cell comprising: first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line.

Claim 17

A row of standard cells operative with first and second voltages, which are different from each other, as a power supply, each cell comprising: first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line.

Claim 18

A reversible standard cell comprising: a logic circuit for executing a desired function; a central voltage source line extending through the center of the standard cell for supplying a first voltage; and a pair of side voltage source lines, extending through edges of the standard cell in parallel to the central voltage source line and located the same distance from the central voltage source line, for supplying a second voltage different from the first voltage, wherein, when combined with other standard cells in order to form a row of standard cells, the central and side voltage source lines are coupled to corresponding lines of adjacent standard cells to form three continuous lines.

Claim 19

A reversible standard cell comprising: a logic circuit for executing a desired function; a central voltage source line extending through the center of the standard cell for supplying a first voltage; and a pair of side voltage source lines, extending through edges of the standard cell in parallel to the central voltage source line and located the same distance from the central voltage source line, for supplying a second voltage different from the first voltage, wherein, when combined with other standard cells in order to form a row of standard cells, the central and side voltage source lines are coupled to corresponding lines of adjacent standard cells to form three continuous lines.

Claim 20

A large scale integrated circuit comprising: a plurality of rows each of which includes a number of standard cells of different types arranged in a line and operative with first and second voltages, adjacent rows of said plurality of rows being separated from each other by a wiring area in which a plurality of electrical connections between standard cells of adjacent rows are made, each standard cell including first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line, wherein said first and second lines have reflectional symmetry with said third line as an axis of symmetry.

Claim 21

A large scale integrated circuit comprising: a plurality of rows each of which includes a number of standard cells of different types arranged in a line and operative with first and second voltages, adjacent rows of said plurality of rows being separated from each other by a wiring area in which a plurality of electrical connections between standard cells of adjacent rows are made, each standard cell including first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line, wherein said first and second lines have reflectional symmetry with said third line as an axis of symmetry.

Claim 22

A large scale integrated circuit as set forth in claim 12, wherein said standard cells are arranged so as to make an input terminal and an output terminal of adjacent standard cells next to each other away from a centerline of said standard cells.

Claim 23

In a large scale integrated circuit comprising a plurality of parallel rows which include a plurality of first standard cells and a plurality of second standard cells arranged in a line and operative with first and second voltages, adjacent rows of said rows being separated from each other by a wiring area in which wirings are formed to make electrical connections between respective standard cells on adjacent rows, said first standard cells including flip-flops and arranged on one of said rows, said second standard cells including circuit elements other than flip-flops and arranged on another of said rows, said first standard cells comprising: first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent first standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line, said first and second lines having reflectional symmetry with said third line as an axis of symmetry, each of said second standard cells comprising: a fourth line located near a first edge of a second standard cell for supplying said first voltage, said fourth line being coupled to corresponding lines of adjacent standard cells to form a continuous line; and a fifth line located near a second edge of said second standard cell opposite said first edge for supplying said second voltage, said fifth line being coupled to corresponding lines of adjacent standard cells to form a continuous line.

Claim 24

In a large scale integrated circuit comprising a plurality of parallel rows which include a plurality of first standard cells and a plurality of second standard cells arranged in a line and operative with first and second voltages, adjacent rows of said rows being separated from each other by a wiring area in which wirings are formed to make electrical connections between respective standard cells on adjacent rows, said first standard cells including flip-flops and arranged on one of said rows, said second standard cells including circuit elements other than flip-flops and arranged on another of said rows, said first standard cells comprising: first and second lines both for the same purpose of supplying said first voltage, said first and second lines being coupled to corresponding lines of adjacent first standard cells to form two continuous lines; and a third line located between said first and second lines for supplying said second voltage, said third line being coupled to corresponding lines of adjacent standard cells to form a continuous line, said first and second lines having reflectional symmetry with said third line as an axis of symmetry, each of said second standard cells comprising: a fourth line located near a first edge of a second standard cell for supplying said first voltage, said fourth line being coupled to corresponding lines of adjacent standard cells to form a continuous line; and a fifth line located near a second edge of said second standard cell opposite said first edge for supplying said second voltage, said fifth line being coupled to corresponding lines of adjacent standard cells to form a continuous line.