Patent US5673227A successfully refreshed from Google Patents.
US5673227A
Expired / Lapsed
US
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Integrated circuit memory with multiplexed redundant column data path
Assignee: NXP USA Inc
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Filing: 1996-05-14
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Granted: 1997-09-30
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Expires: 2016-05-14
Abstract
Abstract An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the memory (10). A redundant multiplexer (24) is coupled to the redundant column (20) and to a top redundant global data line (36) and a bottom redundant global data line (34). Data is routed between the redundant columns (20) and the I/O blocks (49, 70) via the top and bottom redundant global data lines (36, 34) to effectively shorten the redundant global data line, thereby reducing the amount of redundant data line load capacitance. A fuse circuit (50) is used to program which of the top or bottom global data lines (36, 34) replaces a defective data path. This arrangement permits increased redundant array efficiency while achieving the required performance goals.
Inventors
- 👤 Bruce E. Engles
- 👤 Daniel C. Knightly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C29/00; G11C29/70; G11C29/78; G11C29/80
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
132 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a redundant column of memory cells; a first data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for receiving data from the redundant column; a second data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for receiving data from the redundant column; and a redundant multiplexer, coupled to the first and second data line portions, for determining which of the first or second data line portions is to receive the data from the redundant column.
Claim 2
Dependent Claim
132 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a redundant column of memory cells; a first data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for receiving data from the redundant column; a second data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for receiving data from the redundant column; and a redundant multiplexer, coupled to the first and second data line portions, for determining which of the first or second data line portions is to receive the data from the redundant column.
Claim 3
Dependent Claim
22 words
The integrated circuit memory of claim 1, wherein the first and second peripheries are arranged on opposite sides of the memory array.
Claim 4
Dependent Claim
43 words
The integrated circuit memory of claim 2, wherein the first data line portion is coupled to a first output portion located at the first periphery and the second data line portion is coupled to a second output portion located at the second periphery.
Claim 5
Dependent Claim
36 words
The integrated circuit memory of claim 3, further comprising: a fuse circuit, coupled to the redundant multiplexer, for providing a control signal for determining which of the first or second data line portions receives the data.
Claim 6
Dependent Claim
16 words
The integrated circuit memory of claim 1, wherein the redundant column includes four contiguous redundant columns.
Claim 7
Dependent Claim
20 words
The integrated circuit memory of claim 1, wherein the first or second data line portions each provide differential data signals.
Claim 8
Dependent Claim
46 words
The integrated circuit memory of claim 1, wherein first or second data line portions both receive data from the redundant column during a read cycle of the integrated circuit memory and provide data to the redundant column during a write cycle of the integrated circuit memory.
Claim 9
Dependent Claim
132 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a redundant column of memory cells; a first data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for receiving data to the redundant column; a second data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to the redundant column; and a redundant multiplexer, coupled to the first and second data line portions, for determining which of the first or second data line portions is to provide the data to the redundant column.
Claim 10
Dependent Claim
132 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a redundant column of memory cells; a first data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for receiving data to the redundant column; a second data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to the redundant column; and a redundant multiplexer, coupled to the first and second data line portions, for determining which of the first or second data line portions is to provide the data to the redundant column.
Claim 11
Dependent Claim
22 words
The integrated circuit memory of claim 8, wherein the first and second peripheries are arranged on opposite sides of the memory array.
Claim 12
Dependent Claim
43 words
The integrated circuit memory of claim 9, wherein the first data line portion is coupled to a first output portion located at the first periphery and the second data line portion is coupled to a second output portion located at the second periphery.
Claim 13
Dependent Claim
36 words
The integrated circuit memory of claim 10, further comprising: a fuse circuit, coupled to the redundant multiplexer, for providing a control signal for determining which of the first or second data line portions receives the data.
Claim 14
Dependent Claim
16 words
The integrated circuit memory of claim 9, wherein the redundant column includes four contiguous redundant columns.
Claim 15
Dependent Claim
20 words
The integrated circuit memory of claim 9, wherein the first or second data line portions each provide differential data signals.
Claim 16
Dependent Claim
52 words
The integrated circuit memory of claim 9, wherein first or second data line portions each can receive data from the redundant column during a read cycle of the integrated circuit memory and provide data to the redundant column during a write cycle of the integrated circuit memory based on a fuse data.
Claim 17
Dependent Claim
172 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a plurality of global data lines, coupled to the memory array, for providing data to, and receiving data from, the memory array; a redundant column of memory cells; a first redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for providing data to and receiving data from the redundant column; a second redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to and receiving from data from the redundant column; and a redundant multiplexer, coupled to the first and second redundant data line portions, for determining which of the first or second redundant data line portions is to receive the data from, or provide the data to the redundant column.
Claim 18
Dependent Claim
172 words
An integrated circuit memory, comprising: a memory array comprising a plurality of memory cells organized in rows and columns; a plurality of global data lines, coupled to the memory array, for providing data to, and receiving data from, the memory array; a redundant column of memory cells; a first redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a first periphery of the integrated circuit memory, for providing data to and receiving data from the redundant column; a second redundant data line portion, positioned adjacent to the memory array and the redundant column and disposed from the redundant column to a second periphery of the integrated circuit memory, for providing data to and receiving from data from the redundant column; and a redundant multiplexer, coupled to the first and second redundant data line portions, for determining which of the first or second redundant data line portions is to receive the data from, or provide the data to the redundant column.
Claim 19
Dependent Claim
22 words
The integrated circuit memory of claim 15, wherein the first and second peripheries are arranged on opposite ends of the memory array.
Claim 20
Dependent Claim
45 words
The integrated circuit memory of claim 15, wherein the first redundant data line portion is coupled to a first output portion located at the first periphery and the second redundant data line portion is coupled to a second output portion located at the second periphery.
Claim 21
Dependent Claim
37 words
The integrated circuit memory of claim 17, further comprising: a fuse circuit, coupled to the redundant multiplexer, for providing a control signal for determining which of the first or second redundant data line portions receives the data.
Claim 22
Dependent Claim
16 words
The integrated circuit memory of claim 15, wherein the redundant column includes four contiguous redundant columns.
Claim 23
Dependent Claim
28 words
The integrated circuit memory of claim 15, wherein the plurality of global data lines and the first or second redundant data line portions each provide differential data signals.
Claim 24
Dependent Claim
21 words
The integrated circuit memory of claim 1, wherein the redundant column is located approximately in the center of the memory array.
Claim 25
Dependent Claim
21 words
The integrated circuit memory of claim 8, wherein the redundant column is located approximately in the center of the memory array.
Claim 26
Dependent Claim
21 words
The integrated circuit memory of claim 15, wherein the redundant column is located approximately in the center of the memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |