Memory with column redundancy and localized column redundancy control signals

Claim 2

A memory comprising: a left array having a top and a bottom; a left array of redundant columns below said bottom of said left array; a right array having a top and a bottom; a right array of redundant columns below said bottom of said right array; a read global data line coupled to said left array and to said right array and disposed therebetween, for reading data from said left and right arrays; a redundant read global data line coupled to said left and right arrays of redundant columns and disposed therebetween, for reading data from said left array of redundant columns and said right array of redundant columns; top read means, coupled to said read global data line and to said redundant read global data line and disposed above said top of said left and right arrays, for receiving a first fuse signal, and in response, selectively coupling a first data signal, from one of said read global data line and said redundant read global data line; and bottom read means, coupled to said read global data line and to said redundant read global data line and disposed below said bottom of said left and said right redundant arrays, for receiving a second fuse signal, and in response, selectively coupling a second data signal from one of said read global data line and said redundant read global data line.

Claim 3

The memory of claim 1, further comprising a second read global data line coupled to said left and right arrays and disposed therebetween and substantially parallel to said read global data line, for conducting signals complementary to said read global data line.

Claim 4

A memory comprising: a left array having a top and a bottom; a left array of redundant columns below said bottom of said left array; a right array having a top and a bottom; a right array of redundant columns below said bottom of said right array; a left write global data line disposed left of and coupled to said left array; a right write global data disposed right of and coupled to said right array; a left redundant write global data line disposed left of and coupled to said left array of redundant columns; a right redundant write global data line disposed right of coupled to said right array of redundant columns; left write means for receiving a first fuse signal and in response, selectively coupling a first data input signal to one of said left write global data line and said left redundant write global data line; and right write means for receiving a second fuse signal and in response, selectively coupling a second data input signal to one of said right global data line and said right redundant global data line.

Claim 5

A memory comprising: a left array having a top and a bottom; a left array of redundant columns below said bottom of said left array; a right array having a top and a bottom; a right array of redundant columns below said bottom of said right array; a left write global data line disposed left of and coupled to said left array; a right write global data disposed right of and coupled to said right array; a left redundant write global data line disposed left of and coupled to said left array of redundant columns; a right redundant write global data line disposed right of coupled to said right array of redundant columns; left write means for receiving a first fuse signal and in response, selectively coupling a first data input signal to one of said left write global data line and said left redundant write global data line; and right write means for receiving a second fuse signal and in response, selectively coupling a second data input signal to one of said right global data line and said right redundant global data line.

Claim 6

The memory of claim 3, wherein said left write means comprises a top left write means and a bottom left write means, and said right write means comprises a top right write means and a bottom right write means.

Claim 7

The memory of claim 3, further comprising: a read global data line coupled to said left array and to said right array and disposed therebetween, for reading data from said left and right arrays; a redundant read global data line coupled to said left and right arrays of redundant columns and disposed therebetween, for reading data from said left array of redundant columns and said right array of redundant columns; top read means coupled to said read global data line and to said redundant read global data line and disposed above said top of said left and right arrays, for receiving a third fuse signal and in response, selectively coupling a first data signal conducted by one of said read global data line and said redundant read global data line; and bottom read means coupled to said read global data line and to said redundant read global data line and disposed below said bottom of said left and said right redundant arrays, for receiving a fourth fuse signal and in response, selectively coupling a second data signal from one of said read global data line and said redundant read global data line.

Claim 8

A memory comprising: an array of memory elements organized in rows and columns; a redundant array of redundant columns; pluralities of read and write global data lines coupled to said array; pluralities of redundant read and write global data lines coupled to said redundant array; an address comparator including address fuse means for providing a plurality of defective address signals in response to an input address and a corresponding plurality of fuse signals; write means, coupled to, for selectively coupling an input data signal to a selected one of said redundant write global data lines in response to said defective address signals during a write cycle; and read means coupled to for selectively coupling an output data signal to a selected one of said redundant read global data lines in response to said defective address signals during a read cycle.

Claim 9

A memory comprising: an array of memory elements organized in rows and columns; a redundant array of redundant columns; pluralities of read and write global data lines coupled to said array; pluralities of redundant read and write global data lines coupled to said redundant array; an address comparator including address fuse means for providing a plurality of defective address signals in response to an input address and a corresponding plurality of fuse signals; write means, coupled to, for selectively coupling an input data signal to a selected one of said redundant write global data lines in response to said defective address signals during a write cycle; and read means coupled to for selectively coupling an output data signal to a selected one of said redundant read global data lines in response to said defective address signals during a read cycle.

Claim 10

A memory having a read mode and a write mode, comprising: a plurality of arrays, each comprising a plurality of intersecting rows and columns of memory cells; a plurality of sets of write global data line pairs, each set coupled to a corresponding array for carrying data to selected columns of said corresponding array; a plurality of sets of read global data line pairs, each set coupled to an array, for carrying data from selected columns of said array; a plurality of redundant columns of memory cells; a plurality of sets of redundant write global data line pairs, each coupled to a corresponding redundant column, for carrying data to said redundant columns; a plurality of sets of redundant read global data line pairs, each coupled to said redundant columns for carrying data from said redundant columns; comparator means for detecting when a defective column in one of said arrays is to be replaced by a redundant column; a plurality of write fuse means for selecting one of said redundant columns to replace a defective column when the memory is in the write mode; a plurality of write means, each coupled to a corresponding one of said sets of write global data line pairs, a corresponding one of said sets of redundant write global data line pairs, a corresponding one of said write fuse means, and to said comparator means for selectively writing data onto one of said write global data line pairs, and said redundant write global data line pairs in response to said comparator means detecting a defective column when the memory is in the write mode; a plurality of read fuse means for selecting which redundant column is to replace a defective column when the memory is in the read mode; and a plurality of read means, each coupled to a corresponding one of said sets of read global data line pairs, a corresponding one of said sets of redundant read global data line pairs, a corresponding one of said read fuse means, and to said comparator means for selectively reading data from one of said read global data line pairs and said redundant read global data line pairs in response to said comparator means detecting a defective column when the memory is in the read mode.

Claim 11

A memory having a read mode and a write mode, comprising: a plurality of arrays, each comprising a plurality of intersecting rows and columns of memory cells; a plurality of sets of write global data line pairs, each set coupled to a corresponding array for carrying data to selected columns of said corresponding array; a plurality of sets of read global data line pairs, each set coupled to an array, for carrying data from selected columns of said array; a plurality of redundant columns of memory cells; a plurality of sets of redundant write global data line pairs, each coupled to a corresponding redundant column, for carrying data to said redundant columns; a plurality of sets of redundant read global data line pairs, each coupled to said redundant columns for carrying data from said redundant columns; comparator means for detecting when a defective column in one of said arrays is to be replaced by a redundant column; a plurality of write fuse means for selecting one of said redundant columns to replace a defective column when the memory is in the write mode; a plurality of write means, each coupled to a corresponding one of said sets of write global data line pairs, a corresponding one of said sets of redundant write global data line pairs, a corresponding one of said write fuse means, and to said comparator means for selectively writing data onto one of said write global data line pairs, and said redundant write global data line pairs in response to said comparator means detecting a defective column when the memory is in the write mode; a plurality of read fuse means for selecting which redundant column is to replace a defective column when the memory is in the read mode; and a plurality of read means, each coupled to a corresponding one of said sets of read global data line pairs, a corresponding one of said sets of redundant read global data line pairs, a corresponding one of said read fuse means, and to said comparator means for selectively reading data from one of said read global data line pairs and said redundant read global data line pairs in response to said comparator means detecting a defective column when the memory is in the read mode.

Claim 12

The memory of claim 7, wherein each redundant column is a set of four contiguous redundant columns.

Claim 13

The memory of claim 7, wherein said plurality of arrays comprises a first array and a second array, and wherein said plurality of redundant columns comprises a first plurality of redundant columns located at a bottom of said first array and a second plurality of redundant columns located at a bottom of said second array.

Claim 14

The memory of claim 9, wherein said first plurality of redundant columns is for replacing defective columns in said first array and said second plurality of redundant columns is for replacing defective columns in said second array.

Claim 15

The memory of claim 7, wherein each of said write fuse means provides a DC logic signal to write means corresponding thereto when a fusible link in said write fuse means is blown to indicate which redundant column is to replace a defective column.

Claim 16

The memory of claim 11, further comprising a plurality of redundant write generators, each coupled to a corresponding write means and to said comparator means, for receiving said DC logic signal and providing a control signal to deselect a defective column to prevent data from being written on the defective column when the memory is in write mode.

Claim 17

The memory of claim 7, wherein each read fuse means provides a DC logic signal to a read means corresponding thereto when a fusible link in said read fuse means is blown to indicate which redundant column is to replace a defective column.

Claim 18

The memory of claim 13, further comprising a plurality of redundant read generators, each coupled to a read means and to said comparator means, for receiving said DC logic signal and for deselecting a defective column to prevent data from being read from the defective column when the memory is in read mode.

Claim 19

A memory having a read mode and a write mode comprising: a left and a right array of memory cells each comprising a plurality of blocks of intersecting rows and columns of memory cells; said left array having a top portion and a bottom portion and said right array having a top portion and a bottom portion; four sets of write global data line pairs, each set of write global data line pairs coupled to corresponding ones of top and bottom portions of said left and right arrays for carrying data to selected columns of said portions of said array; four sets of read global data line pairs, each set of read global data line pairs coupled to corresponding ones of top and bottom portions of said left and right arrays for carrying data from selected columns of said portion of said array; a left plurality of sets of redundant columns of memory cells located at the bottom of said left array, for replacing defective columns in said left array; a right plurality of sets of redundant columns of memory cells located at the bottom of said right array, for replacing defective columns in said right array; a plurality of sets of redundant write global data line pairs, each coupled to a corresponding redundant column for carrying data to said redundant column; a plurality of redundant read global data line pairs, each coupled to a corresponding redundant column for carrying data from said redundant column; comparator means for detecting when a defective column in said left or right array is to be replaced by a redundant column; a plurality of write fuses for selecting one of said redundant columns to replace a defective column when the memory is in the write mode; a plurality of write means, each coupled to a corresponding one of said sets of write global data line pairs, a corresponding one of said sets of redundant write global data line pairs, a corresponding one of said write fuses, and to said comparator means, for writing data onto one of said write global data line pairs, and said redundant write global data line pairs in response to said comparator means detecting a defective column when the memory is in the write mode; a plurality of read fuses for selecting which of said redundant columns is to replace a defective column when the memory is in the read mode; and a plurality of read means, each coupled to a corresponding one of said sets of read global data line pairs, a corresponding one of said redundant read global data line pairs, a corresponding one of said read fuses and to said comparator means for reading data from one of said read global data line pairs, and said redundant read global data line pairs in response to said comparator means detecting a defective column when the memory is in the read mode.

Claim 20

A memory having a read mode and a write mode comprising: a left and a right array of memory cells each comprising a plurality of blocks of intersecting rows and columns of memory cells; said left array having a top portion and a bottom portion and said right array having a top portion and a bottom portion; four sets of write global data line pairs, each set of write global data line pairs coupled to corresponding ones of top and bottom portions of said left and right arrays for carrying data to selected columns of said portions of said array; four sets of read global data line pairs, each set of read global data line pairs coupled to corresponding ones of top and bottom portions of said left and right arrays for carrying data from selected columns of said portion of said array; a left plurality of sets of redundant columns of memory cells located at the bottom of said left array, for replacing defective columns in said left array; a right plurality of sets of redundant columns of memory cells located at the bottom of said right array, for replacing defective columns in said right array; a plurality of sets of redundant write global data line pairs, each coupled to a corresponding redundant column for carrying data to said redundant column; a plurality of redundant read global data line pairs, each coupled to a corresponding redundant column for carrying data from said redundant column; comparator means for detecting when a defective column in said left or right array is to be replaced by a redundant column; a plurality of write fuses for selecting one of said redundant columns to replace a defective column when the memory is in the write mode; a plurality of write means, each coupled to a corresponding one of said sets of write global data line pairs, a corresponding one of said sets of redundant write global data line pairs, a corresponding one of said write fuses, and to said comparator means, for writing data onto one of said write global data line pairs, and said redundant write global data line pairs in response to said comparator means detecting a defective column when the memory is in the write mode; a plurality of read fuses for selecting which of said redundant columns is to replace a defective column when the memory is in the read mode; and a plurality of read means, each coupled to a corresponding one of said sets of read global data line pairs, a corresponding one of said redundant read global data line pairs, a corresponding one of said read fuses and to said comparator means for reading data from one of said read global data line pairs, and said redundant read global data line pairs in response to said comparator means detecting a defective column when the memory is in the read mode.

Claim 21

The memory of claim 15 wherein each set of redundant columns comprises four contiguous redundant columns.

Claim 22

The memory of claim 15, wherein each write fuse provides a DC logic signal to a write means corresponding thereto when a fusible link in said write fuse is blown to indicate which redundant column is to replace a defective column.

Claim 23

The memory of claim 17, further comprising a plurality of redundant write generators, each coupled to a corresponding one of said write means and to said comparator means, for receiving said DC logic signal and providing a control signal to deselect a defective column to prevent data from being written onto the defective column when the memory is in the write mode.

Claim 24

The memory of claim 15, wherein each read fuse provides a DC logic signal to a read means corresponding thereto when a fusible link in said read fuse is blown to indicate which redundant column is to replace a defective column.

Claim 25

The memory of claim 19, further comprising a plurality of redundant read generators, each coupled to a corresponding one of said read means and to said comparator means, for receiving said DC logic signal and providing a control signal to deselect a defective column to prevent data from being read from the defective column when the memory is in read the mode.