US5673221A — Circuit and method for reading a memory cell that…

Claim 1

Independent Claim 251 words

A sense circuit for reading a memory cell that can store one of a number of data levels, said number greater than two, and that can provide on an output terminal one of a number of signal levels that each identify a corresponding one of said data levels, said one signal level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and an output terminal; a successive approximation register having an input terminal coupled to said output terminal of said comparator, an output terminal that provides said stored data level, and a control output terminal; and a reference-signal generator having a control input terminal that is coupled to said control output terminal of said successive approximation register, an output terminal that is coupled to said second input terminal of said comparator, an offset-reference generator that generates an offset-reference value, a number of reference generators that each generate a reference value substantially equal to one of said signal levels, and a switch circuit that is coupled to said control input terminal, said switch circuit operable to provide said offset-reference value on said output terminal of said reference-signal generator when said successive approximation register selects none of said reference values, and operable to provide on said output terminal of said reference-signal generator a sum of said offset-reference value and one of said reference values selected by said successive approximation register.

Claim 2

Dependent Claim 251 words

A sense circuit for reading a memory cell that can store one of a number of data levels, said number greater than two, and that can provide on an output terminal one of a number of signal levels that each identify a corresponding one of said data levels, said one signal level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and an output terminal; a successive approximation register having an input terminal coupled to said output terminal of said comparator, an output terminal that provides said stored data level, and a control output terminal; and a reference-signal generator having a control input terminal that is coupled to said control output terminal of said successive approximation register, an output terminal that is coupled to said second input terminal of said comparator, an offset-reference generator that generates an offset-reference value, a number of reference generators that each generate a reference value substantially equal to one of said signal levels, and a switch circuit that is coupled to said control input terminal, said switch circuit operable to provide said offset-reference value on said output terminal of said reference-signal generator when said successive approximation register selects none of said reference values, and operable to provide on said output terminal of said reference-signal generator a sum of said offset-reference value and one of said reference values selected by said successive approximation register.

Claim 3

Dependent Claim 93 words

The sense circuit of claim 1 wherein: said signal levels include a first signal level that is the lowest of all of said signal levels, a second signal level that is higher than said first signal level and lower than all of the other signal levels, and a third signal level that is the highest of all of said signal levels; said offset-reference value is between said first and second signal levels; and none of said reference generators generate reference values equal to said first signal level and said third signal level respectively.

Claim 4

Dependent Claim 17 words

The sense circuit of claim 2 wherein said first signal level has a value equal to zero.

Claim 5

Dependent Claim 28 words

The sense circuit of claim 1 wherein said signal levels, offset-reference value, and reference values are signal voltage levels, an offset-reference voltage value, and reference voltage values, respectively.

Claim 6

Dependent Claim 28 words

The sense circuit of claim 1 wherein said signal levels, offset-reference value, and reference values are signal current levels, an offset-reference current value, and reference current values, respectively.

Claim 7

Dependent Claim 51 words

The sense circuit of claim 1 wherein: said signal levels, offset-reference value, and reference values are signal current levels, an offset-reference current value, and reference current values, respectively; and said reference generators each include a nonvolatile memory cell that is programmed to provide an associated one of said reference current values.

Claim 8

Dependent Claim 29 words

The sense circuit of claim 1 wherein said successive approximation register selects at most one of said reference values for said reference-signal generator to sum with said offset-reference value.

Claim 9

Independent Claim 178 words

A method for reading a memory cell, comprising: storing in said memory cell one of a plurality of data levels, said plurality greater than two; associating each of said data levels with a different one of a plurality of signal levels; providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data level; generating an offset-reference value; generating a plurality of reference values that are each approximately equal to one of said signal levels; summing said offset-reference value with a first value of a group of values including said reference values and zero to generate a sum; comparing said signal level on said output terminal with said sum; adding said offset-reference value to a second value of said group of values to update said sum, said second value being within a range of said group of values, said range including the one of said group of values that is approximately equal to said signal level; and repeating said comparing and adding until said signal level is identified.

Claim 10

Independent Claim 178 words

A method for reading a memory cell, comprising: storing in said memory cell one of a plurality of data levels, said plurality greater than two; associating each of said data levels with a different one of a plurality of signal levels; providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data level; generating an offset-reference value; generating a plurality of reference values that are each approximately equal to one of said signal levels; summing said offset-reference value with a first value of a group of values including said reference values and zero to generate a sum; comparing said signal level on said output terminal with said sum; adding said offset-reference value to a second value of said group of values to update said sum, said second value being within a range of said group of values, said range including the one of said group of values that is approximately equal to said signal level; and repeating said comparing and adding until said signal level is identified.

Claim 11

Dependent Claim 18 words

The method of claim 8, further comprising generating a digital value that corresponds to said stored data level.

Claim 12

Dependent Claim 61 words

The method of claim 8 wherein: said associating includes associating each of said data levels with a different one of a plurality of current levels; said generating an offset-reference value includes generating an offset-reference current; and said generating a plurality of reference values includes generating a plurality of reference currents that are each approximately equal to one of said current levels.

Claim 13

Dependent Claim 107 words

The method of claim 8 wherein: said signal levels include a first signal level that is the least of all of said signal levels, a second signal level that is greater than said first signal level and less than all of the remaining signal levels, and a third signal level that is the greatest of all of said signal levels; said generating an offset-reference value includes generating said offset-reference value between said first and second signal levels; and said generating a plurality of reference values includes generating said reference values each equal to a different one of said signal levels except said first and third signal levels.

Claim 14

Dependent Claim 32 words

The method of claim 8 wherein said summing and said adding respectively included summing with and adding to said offset-reference value no more than one of said reference values at a time.

Claim 15

Dependent Claim 241 words

A sense circuit for reading a first memory cell that can store one of a first number of data levels, said first number greater than two, and that can provide on an output terminal one of said first number of current levels that each identify a corresponding one of said data levels, said one current level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and an output terminal; a successive approximation register having an input terminal coupled to said output terminal of said comparator, an output terminal that provides said stored data level, and a control output terminal; and a switch circuit having a control input terminal that is coupled to said control output terminal, an output terminal that is coupled to said second input terminal of said comparator, and at least one switch having a control terminal coupled to said control input terminal, a first path terminal coupled to said output terminal of said switch circuit, and a second path terminal; an offset-reference-current generator having an output terminal coupled to said output terminal of said switch circuit; and at least one reference-current generator that generates a reference current that is substantially equal to one of said current levels and that has an output terminal coupled to said second path terminal of said at least one switch.

Claim 16

Dependent Claim 241 words

A sense circuit for reading a first memory cell that can store one of a first number of data levels, said first number greater than two, and that can provide on an output terminal one of said first number of current levels that each identify a corresponding one of said data levels, said one current level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and an output terminal; a successive approximation register having an input terminal coupled to said output terminal of said comparator, an output terminal that provides said stored data level, and a control output terminal; and a switch circuit having a control input terminal that is coupled to said control output terminal, an output terminal that is coupled to said second input terminal of said comparator, and at least one switch having a control terminal coupled to said control input terminal, a first path terminal coupled to said output terminal of said switch circuit, and a second path terminal; an offset-reference-current generator having an output terminal coupled to said output terminal of said switch circuit; and at least one reference-current generator that generates a reference current that is substantially equal to one of said current levels and that has an output terminal coupled to said second path terminal of said at least one switch.

Claim 17

Dependent Claim 163 words

A sense circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2 n (n>=2) different programming levels, comprising biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell generates a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of said programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator, characterized in that the variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of said plurality of cell current values.

Claim 18

Dependent Claim 163 words

A sense circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2 n (n>=2) different programming levels, comprising biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell generates a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of said programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator, characterized in that the variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of said plurality of cell current values.

Claim 19

Dependent Claim 98 words

A sense circuit according to claim 14, characterized in that said offset current generator generates an offset current intermediate between the lowest cell current value of said plurality of cell current values and the second lowest cell current value that is higher than said lowest cell current value and is lower than all of the other cell current values, and each one of said m-2 distinct current generators generates a current equal to one of said cell current values except said lowest cell current value and the highest cell current value of said plurality of cell current values.

Claim 20

Dependent Claim 43 words

A sense circuit according to claim 15, characterized in that each of said m-2 current generators comprises a reference non-volatile memory cell programmed in one of said m programming levels, except the programming levels corresponding to said lowest and highest cell current values.

Claim 21

Dependent Claim 122 words

A sense circuit according to claim 15, characterized in that the successive approximation register comprises a sequential network which, starting from a predetermined initial state causing the variable reference current generator to generate a reference current with a value comprised between said lowest and highest cell current values dichotomizing the plurality of cell current values, evolves through a succession of states, each one determined by the preceding state and by the output signal of the current comparator, each state of the sequential network causing the variable reference current generator to generate a respective reference current with value comprised between a minimum value and a maximum value of a sub-plurality of the plurality of cell current values to which the cell current belongs.

Claim 22

Dependent Claim 31 words

A sense circuit according to claim 17, characterized in that in each one of said states of the sequential network at most one of the m-2 distinct current generators is activated.

Claim 23

Dependent Claim 28 words

A sense circuit according to claim 18, characterized in that said sequential network automatically presets to said initial state after sensing of a memory cell has been completed.

Claim 24

Dependent Claim 123 words

A sense circuit according to claim 17 for sensing four-level non-volatile memory cells, the variable reference current generator comprising an offset current generator, a first activatable current generator and a second activatable current generator, characterized in that the sequential network comprises two delay-type flip-flops, a first flip-flop having a data output controlling the activation of the first activatable current generator and a data input connected to a complemented data output of the first flip-flop, a second flip-flop having a data output controlling the activation of the second activatable current generator and a data input connected to an output of a NOR gate which is supplied with said complemented data output of the first flip-flop and with the output signal of the current comparator.

Claim 25

Dependent Claim 33 words

A sense circuit according to claim 20, characterized in that said two flip-flops are supplied with a preset signal activated at the circuit power-up to preset the sequential network in said initial state.

Claim 26

Dependent Claim 20 words

The sense circuit of claim 1 wherein said reference-signal generator comprises two fewer reference generators than there are data levels.

Claim 27

Dependent Claim 37 words

The sense circuit of claim 13 wherein said at least one reference-current generator comprises a second memory cell that is similar in structure to said first memory cell and that is programmed to provide said reference current.

Claim 28

Dependent Claim 227 words

A sense circuit for reading a memory cell that can store one of a plurality of data levels, said plurality greater than two, and that can provide on an output terminal one of a plurality of signal levels that each identify a corresponding one of the data levels, said one signal level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and a comparator output terminal; a successive approximation register having an input terminal coupled to said comparator output terminal, a register output terminal that provides said stored data level, and a register control output terminal; and a reference-signal generator having a control input terminal that is coupled to said register control output terminal, an output terminal that is coupled to said second input terminal of said comparator, an offset-reference generator that generates an offset-reference value, a plurality of reference generators that each generate a reference value that substantially equals one of said signal levels, and a switch circuit that is coupled to said control input terminal of said reference-signal generator, said switch circuit operable to provide on said output terminal of said reference-signal generator a sum of said offset reference value and one of said reference values selected by said successive approximation register.

Claim 29

Dependent Claim 227 words

A sense circuit for reading a memory cell that can store one of a plurality of data levels, said plurality greater than two, and that can provide on an output terminal one of a plurality of signal levels that each identify a corresponding one of the data levels, said one signal level on said output terminal identifying said stored data level, said circuit comprising: a comparator having a first input terminal coupled to said output terminal of said memory cell, a second input terminal, and a comparator output terminal; a successive approximation register having an input terminal coupled to said comparator output terminal, a register output terminal that provides said stored data level, and a register control output terminal; and a reference-signal generator having a control input terminal that is coupled to said register control output terminal, an output terminal that is coupled to said second input terminal of said comparator, an offset-reference generator that generates an offset-reference value, a plurality of reference generators that each generate a reference value that substantially equals one of said signal levels, and a switch circuit that is coupled to said control input terminal of said reference-signal generator, said switch circuit operable to provide on said output terminal of said reference-signal generator a sum of said offset reference value and one of said reference values selected by said successive approximation register.

Claim 30

Dependent Claim 36 words

The sense circuit of claim 24 wherein said switch circuit is operable to provide said offset-reference value on said output terminal of said reference-signal generator when said successive approximation register selects none of said reference values.

Claim 31

Independent Claim 166 words

A method for reading a memory cell, comprising: storing in said memory cell one of a plurality of data values, said plurality greater than two; associating each of said data values with a unique one of a plurality of signal levels; providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data value; generating an offset value; generating a plurality of reference values that are each approximately equal to one of said signal levels; summing said offset-reference value with a first one of said reference values to generate a sum; comparing said signal level on said output terminal of said memory cell with said sum; adding said offset value to a second one of said reference values, said second reference value being within a subgroup of said reference values that includes the reference value that is approximately equal to said signal level; and repeating said comparing and adding until said stored data level is determined.

Claim 32

Independent Claim 166 words

A method for reading a memory cell, comprising: storing in said memory cell one of a plurality of data values, said plurality greater than two; associating each of said data values with a unique one of a plurality of signal levels; providing on an output terminal of said memory cell the one of said signal levels that is associated with said stored data value; generating an offset value; generating a plurality of reference values that are each approximately equal to one of said signal levels; summing said offset-reference value with a first one of said reference values to generate a sum; comparing said signal level on said output terminal of said memory cell with said sum; adding said offset value to a second one of said reference values, said second reference value being within a subgroup of said reference values that includes the reference value that is approximately equal to said signal level; and repeating said comparing and adding until said stored data level is determined.

Claim 33

Dependent Claim 16 words

The method of claim 26 wherein one of said reference values is approximately equal to zero.

Claim 34

Dependent Claim 46 words

The method of claim 26 wherein said first reference value is one of said reference values that is closest to a midrange level that equals the sum of the lowest one of said signal levels and the highest one of said signal levels divided by two.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-09-29	2001-03-31	2001-09-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-09-29	2005-03-31	2005-09-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-09-29	2009-03-31	2009-09-30	$7700.00	Window Closed / Lapsed

Circuit and method for reading a memory cell that can store multiple bits of data

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