CMOS current mirror

Claim 2

A current mirror circuit for mirroring current in CMOS integrated circuit technology, comprising: a current mirror arrangement being formed of first and second P-channel MOS transistors (MP32,MP33), the gates of said first and second P-channel MOS transistors (MP32,MP33) being connected together and to the drain of said first P-channel MOS transistor (MP32), said first P-channel MOS transistor (MP32) having its source connected to a power supply potential and its drain connected to a first node (N31), said second P-channel MOS transistor (MP33) having its source connected to the power supply potential and its drain connected to a second node (N34); input current source means (I CS ) for generating a variable current at said first node (N31); a first source follower transistor (MN34) having its gate connected to the first node (N31), its drain connected to the power supply potential, and its source connected to a third node (N33); a second source follower transistor (MP35) having its source connected to the second node (N34), its gate connected to the third node (N33), and its drain connected to a fourth node (N32); a current sinking transistor (MN31) having its gate and drain connected together and to the fourth node (N32) and its source connected to a ground potential; and load circuit means (212) interconnected between the third node (N33) and the ground potential for receiving current from said first source follower transistor (MN34).

Claim 3

A current mirror circuit as claimed in claim 1, wherein said second source follower transistor (MP35) serves to maintain voltages at the first and second nodes (N31,N34) to be substantially equal so as to precisely mirror current from said first P-channel MOS transistor (MP32) to said second P-channel MOS transistor (MP33).

Claim 4

A current mirror circuit as claimed in claim 1, wherein said load circuit means (212) is comprised of a load transistor (MN36) functioning as a current-sinking transistor and a load resistor (R1).

Claim 5

A current mirror circuit as claimed in claim 3, wherein said load transistor (MN36) has its drain connected to the third node (N33), its gate connected to the fourth node (N32), and its source connected to the ground potential, said load resistor (R1) having its one end connected to the third node (N33) and its other end connected to the ground potential.

Claim 6

A current mirror circuit as claimed in claim 1, wherein said load circuit means (212) is comprised of a single load resistor.

Claim 7

A current mirror circuit as claimed in claim 1, further comprising an output stage formed of a current-sourcing transistor (MP32) and a current-sinking transistor (MN1), said current-sourcing transistor (MP2) having its gate coupled to the first node (N31), said current-sinking transistor (MN1) having its gate coupled to the fourth node (N32).

Claim 8

A current mirror circuit as claimed in claim 1, wherein said first source follower transistor (MN34) is comprised of an N-channel MOS transistor.

Claim 9

A current mirror circuit as claimed in claim 7, wherein said second source follower transistor (MP35) is comprised of a P-channel MOS transistor.

Claim 10

A current mirror circuit as claimed in claim 8, wherein said current-sinking transistor (MN31) is comprised of an N-channel MOS transistor.

Claim 11

In a differential current source driver (500) for use in a networking communication physical layer CMOS integrated circuit device, which includes a pair of identical current source driver circuits (510a, 510b), each of said pair of current source driver circuits comprising: a current mirror arrangement being formed of first and second P-channel MOS transistors (MP32,MP33), the gates of said first and second P-channel MOS transistors (MP32,MP33) being connected together and to the drain of said first P-channel MOS transistor (MP32), said first P-channel MOS transistor (MP32) having its source connected to a power supply potential and its drain connected to a first node (N31), said second P-channel MOS transistor (MP33) having its source connected to the power supply potential and its drain connected to a second node (N34); input current source means (I CS ) for generating a variable current at said first node (N31); a first source follower transistor (MN34) having its gate connected to the first node (N31), its drain connected to the power supply potential, and its source connected to a third node (N33); a second source follower transistor (MP35) having its source connected to the second node (N34), its gate connected to the third node (N33), and its drain connected to a fourth node (N32); a current sinking transistor (MN31) having its gate and drain connected together and to the fourth node (N32) and its source connected to a ground potential; and load circuit means (212) interconnected between the third node (N33) and the ground potential for receiving current from said first source follower transistor (MN34).

Claim 12

In a differential current source driver (500) for use in a networking communication physical layer CMOS integrated circuit device, which includes a pair of identical current source driver circuits (510a, 510b), each of said pair of current source driver circuits comprising: a current mirror arrangement being formed of first and second P-channel MOS transistors (MP32,MP33), the gates of said first and second P-channel MOS transistors (MP32,MP33) being connected together and to the drain of said first P-channel MOS transistor (MP32), said first P-channel MOS transistor (MP32) having its source connected to a power supply potential and its drain connected to a first node (N31), said second P-channel MOS transistor (MP33) having its source connected to the power supply potential and its drain connected to a second node (N34); input current source means (I CS ) for generating a variable current at said first node (N31); a first source follower transistor (MN34) having its gate connected to the first node (N31), its drain connected to the power supply potential, and its source connected to a third node (N33); a second source follower transistor (MP35) having its source connected to the second node (N34), its gate connected to the third node (N33), and its drain connected to a fourth node (N32); a current sinking transistor (MN31) having its gate and drain connected together and to the fourth node (N32) and its source connected to a ground potential; and load circuit means (212) interconnected between the third node (N33) and the ground potential for receiving current from said first source follower transistor (MN34).

Claim 13

In a differential current source driver as claimed in claim 10, wherein said second source follower transistor (MP35) serves to maintain voltages at the first and second nodes (N31,N34) to be substantially equal so as to precisely mirror current from said first P-channel MOS transistor (MP32) to said second P-channel MOS transistor (MP33).

Claim 14

In a differential current source driver as claimed in claim 10, wherein said load circuit means (212) is comprised of a load transistor (MN36) functioning as a current-sinking transistor and a load resistor (R1).

Claim 15

In a differential current source driver as claimed in claim 12, wherein said load transistor (MN36) has its drain connected to the third node (N33), its gate connected to the fourth node (N32), and its source connected to the ground potential, said load resistor (R1) having its one end connected to the third node (N33) and its other end connected to the ground potential.

Claim 16

In a differential current source driver as claimed in claim 10, wherein said load circuit means (212) is comprised of a single load resistor.

Claim 17

In a differential current source driver as claimed in claim 10, further comprising an output stage formed of a current-sourcing transistor (MP32) and a current-sinking transistor (MN1), said current-sourcing transistor (MP2) having its gate coupled to the first node (N31), said current-sinking transistor (MN1) having its gate coupled to the fourth node (N32).

Claim 18

In a differential current source driver as claimed in claim 10, wherein said first source follower transistor (MN34) is comprised of an N-channel MOS transistor.

Claim 19

In a differential current source driver as claimed in claim 16, wherein said second source follower transistor (MP35) is comprised of a P-channel MOS transistor.

Claim 20

In a differential current source driver as claimed in claim 17, wherein said current-sinking transistor (MN31) is comprised of an N-channel MOS transistor.