US5012133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for processing sampled analog electrical signals
Assignee: US Philips Corp
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Filing: 1990-02-13
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Granted: 1991-04-30
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Expires: 2010-02-13
Abstract
Abstract A circuit for processing sampled analog current signals, includes means for combining, in predetermined proportions, the input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and apparatus for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit consists of a plurality of circuit modules, for example, scaling, memory, and integrator modules, each of which may be capable only of processing unidirectional currents. In order to provide easy interconnection of the modules, each module is arranged to receive and deliver bidirectional currents and to generate internally bias currents to enable conversion from bidirectional to unidirectional currents and vice versa. In order to increase the accuracy of current summing at inputs to the modules, the input circuit of the module is arranged as a current conveyor circuit which has a very low input impedance.
Inventors
- 👤 John B. Hughes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:48
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/028
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
90 words
A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising; means for combining, in predetermined proportions, an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal from a combined current produced by the combining means in successive sample periods, whrein the combining means comprises a current summing node connected to an input of a current conveyor circuit.
Claim 2
Dependent Claim
90 words
A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising; means for combining, in predetermined proportions, an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal from a combined current produced by the combining means in successive sample periods, whrein the combining means comprises a current summing node connected to an input of a current conveyor circuit.
Claim 3
Dependent Claim
172 words
A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising; means for combining, in predetermined proportions, an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal from a combined current produced by the combining means in successive sample periods; a plurality of circuit modules, each circuit module having a current input for receiving a bi-directional input signal current and a current output for supplying a bi-directional output signal current, means for adding a bias current to the bi-directional input signal current to produce a uni-directional current for processing by the circuit module and means for subtracting a suitably scaled bias current from the processed uni-directional current to produce a bi-directional signal current at the current output of the circuit module, and in which in at least one of the circuit modules the current input comprises a current conveyor circuit.
Claim 4
Dependent Claim
172 words
A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising; means for combining, in predetermined proportions, an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal from a combined current produced by the combining means in successive sample periods; a plurality of circuit modules, each circuit module having a current input for receiving a bi-directional input signal current and a current output for supplying a bi-directional output signal current, means for adding a bias current to the bi-directional input signal current to produce a uni-directional current for processing by the circuit module and means for subtracting a suitably scaled bias current from the processed uni-directional current to produce a bi-directional signal current at the current output of the circuit module, and in which in at least one of the circuit modules the current input comprises a current conveyor circuit.
Claim 5
Dependent Claim
49 words
A circuit arrangement as claimed in claim 2 wherein at least one current conveyor circuit is a three port network whose terminal characteristics can be represented by a hybrid matrix giving the outputs of the three ports (x,y,z) in terms of their corresponding inputs, the hybrid matrix being ##EQU5##
Claim 6
Dependent Claim
152 words
A circuit arrangement as claimed in claim 3 in which at least one current conveyor circuit comprises a first transistor whose main current conducting path is connected between the input and a second diode connected transistor whose other end is connected to a voltage supply, a third transistor whose main current carrying path is connected between the voltage supply and a fourth diode connected transistor whose other end is connected to an input terminal for the application of a reference potential, and a fifth transistor whose control electrode is connected to control electrodes of the second and third transistors and whose main current conducting path is connected between the supply voltage and the output, where in control electrodes of the first and fourth transistors are commoned, and means for internally generating a cancelling current for cancelling the current through the fourth transistor so that no current is drawn through the input terminal.
Claim 7
Dependent Claim
53 words
A circuit as claimed in claim 4 wherein the means for internally generating the cancelling current comprises a sixth transistor whose control electrode is connected to the control electrode of the second transistor and which is connected to produce the cancelling current, and means for feeding the cancelling current to the fourth transistor.
Claim 8
Dependent Claim
21 words
A circuit arrangement as claimed in claim 5 wherein the means for feeding the cancelling current comprises a current mirror circuit.
Claim 9
Dependent Claim
49 words
A circuit arrangement as claimed in claim 1 wherein at least one current conveyor circuit is a three port network whose terminal characteristics can be represented by a hybrid matrix giving the outputs of the three ports (x,y,z) in terms of their corresponding inputs, the hybrid matrix being ##EQU6##
Claim 10
Dependent Claim
151 words
A circuit arrangement as claimed in claim 7 in which at least one current conveyor circuit comprises a first transistor whose main current conducting path is connected betweeen the input and a second diode connected transistor whose other end is connected to a voltage supply, a third transistor whose main current carrying path is connected between the voltage supply and a fourth diode connected transistor whose other end is connected to an input terminal for the application of a reference potential, and a fifth transistor whose control electrode is connected to control electrodes of the second and third transistors and whose main current conducting path is connected between the supply voltage and the output, wherein control electrodes of the first and fourth transistors are commoned, and means for internally generating a cancelling current for cancelling the current through the fourth transistor so that no current is drawn through the input terminal.
Claim 11
Dependent Claim
53 words
A circuit as claimed in claim 8 wherein the means for internally generating the cancelling current comprises a sixth transistor whose control electrode is connected to the control electrode of the second transistor and which is connected to produce the cancelling current, and means for feeding the cancelling current to the fourth transistor.
Claim 12
Dependent Claim
21 words
A circuit arrangement as claimed in claim 9 wherein the means for feeding the cancelling current comprises a current mirror circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |