Patent US4047777A successfully refreshed from Google Patents.
Patent US5671352A successfully refreshed from Google Patents.
US5671352A
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Error injection to a behavioral model
Assignee: Sun Microsystems Inc
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Filing: 1995-07-07
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Granted: 1997-09-23
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Expires: 2015-07-07
Abstract
Abstract A method and an apparatus for a dynamic error injection mechanism used in conjunction with a behavioral simulator in testing simulated hardware and software, and more particularly the testing of error handling code. In one implementation of the invention, Sun Microsystem's MPSAS (MULTI-PROCESSOR SPARC ARCHITECTURAL SIMULATOR) may be utilized as a behavioral model to implement the present invention. With the present invention, a range of addresses may be specified within which to test such errors. When such a command is issued, MPSAS logs the error and address range. Simulation can then be continued. At the next access to the address range to be tested with for a specific error, the present invention triggers off simulated hardware actions which would be taken in an actual hardware upon its encountering the same error. If the corresponding error handlers are turned on by the software of the present invention, the trap will be taken and the code will vector off to the error handler. This enables an operating system developer to test the error handling code.
Inventors
- 👤 Ramesh Subrahmaniam
- 👤 Elizabeth George
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/2205
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
147 words
A method for testing an error handler on a simulated hardware comprising the steps of: dynamically injecting an error information specifying an address range and an error type into a plurality of simulated components to be tested, each said plurality of simulated components being part of said simulated hardware and having a user interface command coupled to a user interface module, said user interface module accepting said error information from a user while said simulated hardware is running and transmitting said error information to said user interface command for injecting said error type into said address range as specified by said error information transmitted; causing said error type to occur in said address range of said simulated component upon a memory access to any one of said plurality of simulated components having said error information; and determining whether said error handler is correctly handling said error type.
Claim 2
Independent Claim
147 words
A method for testing an error handler on a simulated hardware comprising the steps of: dynamically injecting an error information specifying an address range and an error type into a plurality of simulated components to be tested, each said plurality of simulated components being part of said simulated hardware and having a user interface command coupled to a user interface module, said user interface module accepting said error information from a user while said simulated hardware is running and transmitting said error information to said user interface command for injecting said error type into said address range as specified by said error information transmitted; causing said error type to occur in said address range of said simulated component upon a memory access to any one of said plurality of simulated components having said error information; and determining whether said error handler is correctly handling said error type.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein said step of injecting further comprising the step of using a user interface to receive said error information.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said step of injecting further comprises the step of enabling an error mechanism flag.
Claim 5
Dependent Claim
30 words
The method of claim 1 wherein said step of injecting further comprises the step of parsing said error information and routing said error information to said plurality of simulated components.
Claim 6
Dependent Claim
20 words
The method of claim 4 further comprising the step of logging said error information in said plurality of simulated components.
Claim 7
Dependent Claim
40 words
The method of claim 1 wherein said step of causing further comprises the step of checking each said memory access to determine whether each said memory access is within said address range if an error mechanism flag has been enabled.
Claim 8
Dependent Claim
25 words
The method of claim 6 further comprising the step of setting bits in an error register if said memory access is within said address range.
Claim 9
Dependent Claim
24 words
The method of claim 1 wherein said step of determining further comprising the step of jumping to said error handler if traps are enabled.
Claim 10
Independent Claim
155 words
An apparatus for testing an error handler on a simulated hardware comprising: an error injection mechanism for dynamically injecting an error information including error type and an address range, said error information being dynamically injected into one of a plurality of simulated components of said simulated hardware while said simulated hardware is running, each said plurality of simulated components having a dedicated first user interface module for receiving said error information, said error injection mechanism causing said error type to occur within said address range to test whether said error handler is correctly handling said error type; and a second user interface module for allowing said dynamic injection of said error information into said simulated hardware, said second user interface module accepting said error information from a user while said simulated hardware is running and transmitting said error information to said dedicated first user interface module of any one of said plurality of simulated components.
Claim 11
Independent Claim
155 words
An apparatus for testing an error handler on a simulated hardware comprising: an error injection mechanism for dynamically injecting an error information including error type and an address range, said error information being dynamically injected into one of a plurality of simulated components of said simulated hardware while said simulated hardware is running, each said plurality of simulated components having a dedicated first user interface module for receiving said error information, said error injection mechanism causing said error type to occur within said address range to test whether said error handler is correctly handling said error type; and a second user interface module for allowing said dynamic injection of said error information into said simulated hardware, said second user interface module accepting said error information from a user while said simulated hardware is running and transmitting said error information to said dedicated first user interface module of any one of said plurality of simulated components.
Claim 12
Dependent Claim
21 words
The apparatus of claim 9 wherein said error injection mechanism further comprises an error mechanism flag for enabling an error checker.
Claim 13
Dependent Claim
37 words
The apparatus of claim 9 wherein said error injection mechanism further comprises an error checker for checking whether a memory access being made during an execution of said plurality of simulated components is within said address range.
Claim 14
Dependent Claim
19 words
The apparatus of claim 9 wherein said error injection mechanism further comprises a parser for parsing said error information.
Claim 15
Dependent Claim
27 words
The apparatus of claim 9 wherein said error injection mechanism further comprises a router for routing said error information to the appropriate said plurality of simulated components.
Claim 16
Dependent Claim
26 words
The apparatus of claim 9 wherein said error injection mechanism further comprises an error logger for logging said error information in said plurality of simulated components.
Claim 17
Dependent Claim
174 words
A computer system for testing an error handler on a simulated hardware comprising: a storage element having, an error injection mechanism for dynamically injecting an error information including error type and address range, said error information being dynamically injected into any one of a plurality of simulated components of said simulated hardware while said simulated hardware is running, each said plurality of simulated components having a dedicated first user interface module for receiving said error information, said error injection mechanism causing said error type to occur within said address range to test whether said error handler is correctly handling said error type, and a second user interface module for allowing said dynamic injecting of said error information into said simulated hardware, said second user interface module accepting said error information from said user while said simulated hardware is running and transmitting said error information to said dedicated first user interface module of any one of said plurality of simulated components; and a processor coupled to said storage element for executing said error injection mechanism.
Claim 18
Dependent Claim
174 words
A computer system for testing an error handler on a simulated hardware comprising: a storage element having, an error injection mechanism for dynamically injecting an error information including error type and address range, said error information being dynamically injected into any one of a plurality of simulated components of said simulated hardware while said simulated hardware is running, each said plurality of simulated components having a dedicated first user interface module for receiving said error information, said error injection mechanism causing said error type to occur within said address range to test whether said error handler is correctly handling said error type, and a second user interface module for allowing said dynamic injecting of said error information into said simulated hardware, said second user interface module accepting said error information from said user while said simulated hardware is running and transmitting said error information to said dedicated first user interface module of any one of said plurality of simulated components; and a processor coupled to said storage element for executing said error injection mechanism.
Claim 19
Dependent Claim
21 words
The system of claim 15 wherein said error injection mechanism further comprises an error mechanism flag for enabling an error checker.
Claim 20
Dependent Claim
37 words
The system of claim 15 wherein said error injection mechanism further comprises an error checker for checking whether a memory access being made during an execution of said plurality of simulated components is within said address range.
Claim 21
Dependent Claim
19 words
The system of claim 15 wherein said error injection mechanism further comprises a parser for parsing said error information.
Claim 22
Dependent Claim
27 words
The system of claim 15 wherein said error injection mechanism further comprises a router for routing said error information to the appropriate said plurality of simulated components.
Claim 23
Dependent Claim
26 words
The system of claim 15 wherein said error injection mechanism further comprises an error logger for logging said error information in said plurality of simulated components.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |