Process and circuit arrangement for checking a program in data processing units

Claim 3

The method as claimed in claim 1 where the data processing unit includes means for receiving a start program command for starting the program to be checked, the improvement further comprising: initiating said writing data with false parity signals and then starting said program to be checked only after the completion of the writing data with false parity signals in response to a start program command.

Claim 4

The method as claimed in claim 1 wherein the data processing unit includes means for dynamically assigning certain memory regions to a program and for dynamically releasing the memory regions assigned to a program, the improvement further comprising: writing data with false parity signals into released memory regions upon dynamic release of said memory regions by the program to be checked.

Claim 5

A data processing unit comprising: a read/write memory means having a plurality of memory cells for writing and recalling data words and corresponding parity signals; a central processing unit for manipulating data words recalled from said read/write memory means and writing resulting data in said read/write memory means; a parity generator/parity checker means connected to said read/write memory means and said central processing unit for checking the parity of data words recalled from said read/write memory means against said corresponding parity signal and signaling said central processing unit upon detection of a parity error and for generating the corresponding parity signal for data words to be written into said read/write memory means; an exclusive OR circuit having a first input receiving the parity signal generated by said parity generator/parity checker means and a second input receiving a control signal controlled by said central processing unit and an output connected to said read/write memory means for supplying said parity signal corresponding to a data word to be written into said read/write memory means, whereby the state of said control signal controls whether true or false parity signals are written into said read/write memory means; and an operating system memory having stored therein an operating system for control of said central processing unit for writing data words having false parity signals into at least the memory cells of said read/write memory means to be used by a program to be checked by causing said central processing unit to control the state of said control signal supplied to said second input of said exclusive OR circuit.

Claim 6

A data processing unit comprising: a read/write memory means having a plurality of memory cells for writing and recalling data words and corresponding parity signals; a central processing unit for manipulating data words recalled from said read/write memory means and writing resulting data in said read/write memory means; a parity generator/parity checker means connected to said read/write memory means and said central processing unit for checking the parity of data words recalled from said read/write memory means against said corresponding parity signal and signaling said central processing unit upon detection of a parity error and for generating the corresponding parity signal for data words to be written into said read/write memory means; an exclusive OR circuit having a first input receiving the parity signal generated by said parity generator/parity checker means and a second input receiving a control signal controlled by said central processing unit and an output connected to said read/write memory means for supplying said parity signal corresponding to a data word to be written into said read/write memory means, whereby the state of said control signal controls whether true or false parity signals are written into said read/write memory means; and an operating system memory having stored therein an operating system for control of said central processing unit for writing data words having false parity signals into at least the memory cells of said read/write memory means to be used by a program to be checked by causing said central processing unit to control the state of said control signal supplied to said second input of said exclusive OR circuit.