Multi-stage ROM wherein a cell current of a selected memory cell is compared with a plurality of constant currents when driven to read voltages

Claim 3

A method as claimed in claim 1, further comprising the step of judging on or off of said selected memory cell when said selected memory cell is supplied with said second voltage.

Claim 4

A multi-stage semicondutor memory device comprising: a plurality of transistor memory cells, each given a selected threshold level selected from a zeroth threshold level, a first threshold level higher than said zeroth threshold level, a second threshold level higher than said first threshold level, and a third threshold level higher than said second threshold level; selecting means responsive to address signals for selecting a selected memory cell from said transistor memory cells; supply means responsive to a control signal variable between first and second logic levels for supplying said selecting means with a first voltage between said zeroth and said first threshold levels and a second voltage between said second and said third threshold levels while said control signal has said first and said second logic levels, respectively; first judging means for judging on or off of said selected memory cell while said control signal has said first logic level; and second judging means for judging, by comparison between a predetermined constant current and a cell current flowing through said selected memory cell while said control signal has said second logic level, whether or not said selected threshold level is said zeroth threshold level.

Claim 5

A multi-stage semicondutor memory device comprising: a plurality of transistor memory cells, each given a selected threshold level selected from a zeroth threshold level, a first threshold level higher than said zeroth threshold level, a second threshold level higher than said first threshold level, and a third threshold level higher than said second threshold level; selecting means responsive to address signals for selecting a selected memory cell from said transistor memory cells; supply means responsive to a control signal variable between first and second logic levels for supplying said selecting means with a first voltage between said zeroth and said first threshold levels and a second voltage between said second and said third threshold levels while said control signal has said first and said second logic levels, respectively; first judging means for judging on or off of said selected memory cell while said control signal has said first logic level; and second judging means for judging, by comparison between a predetermined constant current and a cell current flowing through said selected memory cell while said control signal has said second logic level, whether or not said selected threshold level is said zeroth threshold level.

Claim 6

A multi-stage semiconductor memory device as claimed in claim 3, wherein said second judging means comprises: primary judging means for judging on or off of said selected memory cell while said control signal has said second logic level; and secondary judging means for judging, by comparison if said selected memory cell is on, whether or not said selected threshold level is said zeroth threshold level.

Claim 7

A multi-stage semiconductor memory device comprising first through N-th word lines and first through M-th digit lines crossing said first through said N-th word lines at cross points, where N and M represent first and second predetermined integers, a plurality of semiconductor memory cells at said cross points, selecting means responsive to address signals for selecting a selected word line from said first through said N-th word lines and a selected digit line from said first through said M-th digit lines, driving means for driving said selected word line to one of first and second voltages, and sensing means for sensing a cell current flowing through said selected digit line, wherein said sensing means compares said cell current with first and second constant currents while said selected word line is driven to said first and said second voltages, respectively.

Claim 8

A multi-stage semiconductor memory device comprising first through N-th word lines and first through M-th digit lines crossing said first through said N-th word lines at cross points, where N and M represent first and second predetermined integers, a plurality of semiconductor memory cells at said cross points, selecting means responsive to address signals for selecting a selected word line from said first through said N-th word lines and a selected digit line from said first through said M-th digit lines, driving means for driving said selected word line to one of first and second voltages, and sensing means for sensing a cell current flowing through said selected digit line, wherein said sensing means compares said cell current with first and second constant currents while said selected word line is driven to said first and said second voltages, respectively.

Claim 9

A multi-stage semiconductor memory device as claimed in claim 5, each of said semiconductor memory cells being given a selected one of zeroth, first, second, and third threshold levels, wherein: said first voltage is between said zeroth and said first threshold levels; said second voltage being between said second and said third threshold levels.

Claim 10

A multi-stage semiconductor memory device as claimed in claim 6, said zeroth threshold level being lower than said first threshold level, said first threshold level being lower than said second threshold level, said second threshold level being lower than said third threshold level, wherein said first constant current is less than said second constant current.

Claim 11

A multi-stage semiconductor memory device as claimed in claim 5, wherein said sensing means compares, while said selected word line is driven to said second voltage, said cell current with said first constant current besides said second constant current.

Claim 12

A multi-stage semiconductor memory device as claimed in claim 8, each of said semiconductor memory cells being given a selected one of zeroth, first, second, and third threshold levels, wherein: said first voltage is between said zeroth and said first threshold levels; said second voltage being between said second and said third threshold levels.

Claim 13

A multi-stage semiconductor memory device as claimed in claim 9, said zeroth threshold level being lower than said first threshold level, said first threshold level being lower than said second threshold level, said second threshold level being lower than said third threshold level, wherein said first constant current is less than said second constant current.

Claim 14

A multi-stage semiconductor memory device as claimed in claim 5, wherein: said sensing means produces a comparison result indicative of a result of comparison of said cell current with said first constant current while said selected word line is driven to said first voltage; said sensing means comparing said cell current, while said selected word line is driven to said second voltage, with one of said first and said second constant currents that is selected based on said comparison result.

Claim 15

A multi-stage semiconductor memory device as claimed in claim 11, each of said semiconductor memory cells being given a selected one of zeroth, first, second, and third threshold levels, wherein: said first voltage is between said zeroth and said first threshold levels; said second voltage being between said second and said third threshold levels.

Claim 16

A multi-stage semiconductor memory device as claimed in claim 12, said zeroth threshold level being lower than said first threshold level, said first threshold level being lower than said second threshold level, said second threshold level being lower than said third threshold level, wherein said first constant current is less than said second constant current.