US5664134A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor for performing a comparison instruction using selective enablement and wired boolean logic
Assignee: Hanger Solutions LLC
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Filing: 1995-02-23
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Granted: 1997-09-02
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Expires: 2015-02-23
Abstract
Abstract A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.
Inventors
- 👤 Michael G. Gallup
- 👤 L. Rodney Goke
- 👤 Robert W. Seaton, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:10
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F9/00; G06F9/06; G06F9/46; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/78; G06F15/80; G06F15/8007; G06F15/8023; G06F15/8053; G06F15/8092; G06F7/544; G06F8/00; G06F8/40; G06F8/41; G06F8/44; G06F8/445; G06F8/447; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30021; G06F9/30036; G06F9/3005; G06F9/30065; G06F9/30072; G06F9/30076; G06F9/30079; G06F9/30083; G06F9/30094; G06F9/30098; G06F9/30101; G06F9/30105; G06F9/30116; G06F9/38; G06F9/3802; G06F9/3812; G06F9/3836; G06F9/3851; G06F9/3867; G06F9/3877; G06F9/3885; G06F9/3887; G06F9/38873; G06F9/3889; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49921
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
260 words
A data processor, comprising: storage means for storing a comparison instruction which specifies a number of bits to be compared; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction; and a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state.
Claim 2
Dependent Claim
260 words
A data processor, comprising: storage means for storing a comparison instruction which specifies a number of bits to be compared; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction; and a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state.
Claim 3
Dependent Claim
33 words
The data processor of claim 1 wherein the data value stored in each of the plurality of enabled processing elements has a predetermined bit width of n, where n is a positive integer.
Claim 4
Dependent Claim
23 words
The data processor of claim 2 wherein the first portion of the data value is a most significant bit of the data value.
Claim 5
Dependent Claim
36 words
The data processor of clam 1 further comprising: a first storage circuit for storing a pIurality of enable values, each of the plurality of enable values corresponding to one of the plurality of enabled processing elements.
Claim 6
Dependent Claim
36 words
The data processor of clam 1 further comprising: a first storage circuit for storing a pIurality of enable values, each of the plurality of enable values corresponding to one of the plurality of enabled processing elements.
Claim 7
Dependent Claim
37 words
The data processor of claim 2 further comprising: a modification circuit for selectively modifying a portion of the plurality of enable values in response to one of the first and second logic states of the comparison conductor.
Claim 8
Dependent Claim
40 words
The data processor of claim 5 wherein one of the plurality of enabled processing elements is enabled to provide the data value stored therein to the comparison conductor when a corresponding one of the plurality of enable values is asserted.
Claim 9
Dependent Claim
37 words
The data processor of claim 5 wherein one of the plurality of enabled processing elements is distilled from participating in execution of the comparison instruction when a corresponding one of the plurality of enable values is negated.
Claim 10
Dependent Claim
31 words
The data processor of claim 5 wherein the plurality of enable values selectively enable the plurality of enabled processing elements to provide the first digital data value to the comparison conductor.
Claim 11
Dependent Claim
118 words
The data processor of claim 8 wherein the modification circuit: leaves one of the plurality of enable values unmodified when the comparison conductor is in the first logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the first logic state, and leaves the one of the plurality of enable values unmodified when the comparison conductor is in the second logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.
Claim 12
Dependent Claim
62 words
The data processor of claim 8 wherein the modification circuit modifies one of the plurality of enable values when the comparison conductor is in the first logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.
Claim 13
Dependent Claim
33 words
The data processor of claim 1 wherein the comparison instruction determines a first portion of the plurality of processing elements which have a maximum value in the first portion of the data value.
Claim 14
Dependent Claim
40 words
The data processor of claim 1 wherein each of the plurality of enabled processing elements further comprises: a logic circuit for complementing the first portion of the data value to provide a first complemented data value to the comparison conductor.
Claim 15
Dependent Claim
34 words
The data processor of claim 12 wherein the comparison instruction determines a first portion of the plurality of enabled processing elements which have a minimum value in the first portion of the data value.
Claim 16
Dependent Claim
18 words
The data processor of claim 12 wherein the first portion of the data value is a sign bit.
Claim 17
Dependent Claim
45 words
The data processor of claim 1 further comprising a control storage circuit for storing a control value, the control value indicating the comparison instruction uses one of a signed operand and an unsigned operand, the control storage circuit being coupled to the instruction execution means.
Claim 18
Dependent Claim
45 words
The data processor of claim 1 further comprising: a switch circuit which is coupled to the comparison conductor; and a first integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the first integrated circuit pin to the comparison conductor.
Claim 19
Dependent Claim
27 words
The data processor of claim 16 wherein the switch circuit selectively couples the first integrated circuit pin to the comparison conductor in response to the comparison instruction.
Claim 20
Dependent Claim
57 words
The data processor of claim 17 wherein the first integrated circuit pin is coupled to a first external integrated circuit pin of an external data processor, the first integrated circuit pin coupling the comparison conductor to the first external integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor.
Claim 21
Dependent Claim
50 words
The data processor of claim 18 wherein the first integrated circuit pin transfers control infomarion when the data processor is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the data processor is in a second mode of operation.
Claim 22
Dependent Claim
24 words
The data processor of claim 16 further comprising a second integrated circuit pin, the second integrated circuit pin being coupled to the switch circuit.
Claim 23
Independent Claim
190 words
A method of comparing a plurality of data values in a data processor, comprising the steps of: receiving a comparison instruction which specifies a number of bits to be compared; decoding the comparison instruction to provide a plurality of control signals; determining which of a plurality of processing elements are enabled, each processing element of an enabled portion of the plurality of processing elements providing a first portion of a data value stored therein to a comparison line; providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state; providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state; and selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements.
Claim 24
Independent Claim
190 words
A method of comparing a plurality of data values in a data processor, comprising the steps of: receiving a comparison instruction which specifies a number of bits to be compared; decoding the comparison instruction to provide a plurality of control signals; determining which of a plurality of processing elements are enabled, each processing element of an enabled portion of the plurality of processing elements providing a first portion of a data value stored therein to a comparison line; providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state; providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state; and selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements.
Claim 25
Dependent Claim
36 words
The method of claim 21 wherein each of the plurality of enable values selectively enable a corresponding one of the enabled portion of the plurality of processing elements to provide the digital data value stored therein.
Claim 26
Dependent Claim
52 words
The method of claim 21 further comprising the step of: negating the one of the plurality of enable bits when the first portion of the data value provided by the corresponding one of the enabled portion of the plurality of processing elements is in a different logic state than the comparison line.
Claim 27
Dependent Claim
56 words
The method of claim 23 further comprising the step of: insuring that one of the plurality of enable bits remains in an asserted state when the first portion of the data value provided by a corresponding one of the enabled portion of the plurality of processing elements in a same logic state as the comparison line.
Claim 28
Dependent Claim
184 words
The method of claim 23 further comprising the steps of: accessing a second portion of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted; providing the second portion of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line; providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the second portion of the data value stored therein in the first logic state; providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the second portion of the data value stored therein in the second logic state; and negating one of the plurality of enable bits when the second portion of the data value is in a different logic state than the comparison line.
Claim 29
Dependent Claim
36 words
The method of claim 21 wherein each of the plurality of data values stored in each one of the plurality of processing elements has a plurality of n bits, where n is a positive integer value.
Claim 30
Dependent Claim
26 words
The method of claim 26 wherein the first portion of each of the plurality of data values is a most significant bit of the data value.
Claim 31
Dependent Claim
240 words
The method of claim 27 further comprising the steps of: i) accessing a next one of the plurality of bits of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted; ii) providing the next one of the plurality of bits of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line; iii) providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the first logic state; iv) providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the second logic state; v) negating one of the plurality of enable values when the next one of the plurality of bits of the data value is in a different logic state than the comparison line; and vi) repeating steps i) through v) for a predetermined number of repetitions as specified by the number of bits to be compared in the comparison instruction.
Claim 32
Dependent Claim
18 words
The method of claim 28 wherein the predetermined number of repetitions is equal to a value of (n-1).
Claim 33
Dependent Claim
18 words
The method of claim 28 wherein the predetermined number of repetitions is less than the value of (n-1).
Claim 34
Dependent Claim
29 words
The method of claim 28 wherein the comparison instruction determines a first portion of the plurality of processing elements which store an unsigned data value having a maximum value.
Claim 35
Dependent Claim
42 words
The method of claim 28 further comprising the step of: inverting the most significant bit of the data value provided by each of the plurality of processing elements before providing the most significant bit of the data value to the comparison line.
Claim 36
Dependent Claim
34 words
The method of claim 32 wherein the comparison instruction determines a second portion of processing elements in the plurality of processing elements which store a two's complement signed data value having a maximum value.
Claim 37
Dependent Claim
42 words
The method of claim 28 further comprising the step of: inverting each of the plurality of bits of the data value provided by each of the plurality of processing elements before providing each of the plurality of bits to the comparison line.
Claim 38
Dependent Claim
32 words
The method of claim 34 wherein the comparison instruction determines a third portion of processing elements in the plurality of processing elements which store an unsigned data value having a minimum value.
Claim 39
Dependent Claim
61 words
The method of claim 28 further comprising the step of: inverting a portion of the plurality of bits of the data value provided by each of the plurality of processing elements before providing the portion of the plurality of bits to the comparison line, the portion of the plurality of bits not including the most significant bit of the data value.
Claim 40
Dependent Claim
34 words
The method of claim 36 wherein the comparison instruction determines a fourth portion of processing elements in the plurality of processing elements which store a two's complement signed data value having a minimum value.
Claim 41
Dependent Claim
325 words
A data processing system, comprising: a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising: storage means for storing a comparison instruction which specifies a number of bits to be compared; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state; and each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors.
Claim 42
Dependent Claim
325 words
A data processing system, comprising: a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising: storage means for storing a comparison instruction which specifies a number of bits to be compared; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state; and each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors.
Claim 43
Dependent Claim
29 words
The data processor of claim 38 wherein the first portion of the data value is equal to the number of bits to be compared specified by the comparison instruction.
Claim 44
Dependent Claim
20 words
The data processing system of claim 38 wherein the array comprises at least one row and at least one column.
Claim 45
Dependent Claim
35 words
The data processing system of claim 40 wherein the first one of the plurality of data processors is in a same row of the array as the second one of the plurality of data processors.
Claim 46
Dependent Claim
35 words
The data processing system of claim 40 wherein the first one of the plurality of data processors is in a same column of the array as the second one of the plurality of data processors.
Claim 47
Dependent Claim
37 words
The data processing system of claim 38 further comprising: a first storage circuit for storing a plurality of enable values, each of the plurality of enable values corresponding to one of the plurality of enabled processing elements.
Claim 48
Dependent Claim
38 words
The data processing system of claim 43 further comprising: a modification circuit for selectively modifying each one of the plurality of enable values in response to one of the first and second logic states of the comparison conductor.
Claim 49
Dependent Claim
36 words
The data processing system of claim 44 wherein each one of the plurality of enabled processing elements participates in execution of the comparison instruction when a corresponding one of the plurality of enable values is asserted.
Claim 50
Dependent Claim
38 words
The data processing system of claim 44 wherein one of the plurality of enabled processing elements is disabled from participating in execution of the comparison instruction when a corresponding one of the plurality of enable values is negated.
Claim 51
Dependent Claim
63 words
The data processing system of claim 44 wherein the modification circuit negates one of the plurality of enable values when the comparison conductor is in the first logic state and the first bit of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.
Claim 52
Dependent Claim
47 words
The data processing system of claim 44 wherein the comparison instruction determines a first portion of the plurality of enabled processing elements in each of an enabled portion of the plurality of data processors which have a maximum value in the first bit of the data value.
Claim 53
Dependent Claim
44 words
The data processing system of claim 44 wherein each one of the plurality of enabled processing elements further comprises: a logic circuit for selectively compIementing at least a portion of the data value to provide a first complemented data value to the comparison conductor.
Claim 54
Dependent Claim
23 words
The data processing system of claim 49 wherein the portion of the data value is a most significant bit of the data value.
Claim 55
Dependent Claim
50 words
The data processing system of claim 38 wherein each of the data processors further comprises: a switch circuit which is coupled to the comparison conductor; and an integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the integrated circuit pin to the comparison conductor.
Claim 56
Dependent Claim
28 words
The data processing system of claim 51 wherein the switch circuit selectively couples the integrated circuit pin to the comparison conductor in response to a global comparison instruction.
Claim 57
Dependent Claim
71 words
The data processing system of claim 52 wherein a first integrated circuit pin of a first one of the plurality of data processors is coupled to a second integrated circuit pin of a second one of the plurality of data processors, the first integrated circuit pin coupling the comparison conductor to the second integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor.
Claim 58
Dependent Claim
63 words
The data processing system of claim 53 wherein the first integrated circuit pin transfers control information when the first one of the plurality of data processors is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the first one of the plurality of data processors is in a second mode of operation.
Claim 59
Dependent Claim
389 words
A data processor, comprising: storage means for storing a comparison instruction; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state; a switch circuit which is coupled to the comparison conductor; and a first integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the first integrated circuit pin to the comparison conductor in response to the comparison instruction, wherein the first integrated circuit pin is coupled to a first external integrated circuit pin of an external data processor, the first integrated circuit pin coupling the comparison conductor to the first external integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor; and wherein the first integrated circuit pin transfers control information when the data processor is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the data processor is in a second mode of operation.
Claim 60
Dependent Claim
389 words
A data processor, comprising: storage means for storing a comparison instruction; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state; a switch circuit which is coupled to the comparison conductor; and a first integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the first integrated circuit pin to the comparison conductor in response to the comparison instruction, wherein the first integrated circuit pin is coupled to a first external integrated circuit pin of an external data processor, the first integrated circuit pin coupling the comparison conductor to the first external integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor; and wherein the first integrated circuit pin transfers control information when the data processor is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the data processor is in a second mode of operation.
Claim 61
Independent Claim
506 words
A method of comparing a plurality of data values in a data processor, comprising the steps of: i) receiving a comparison instruction; ii) decoding the comparison instruction to provide a plurality of control signals; iii) determining which of a plurality of processing elements are enabled, wherein each of the plurality of data values stored in each one of the plurality of processing elements has a plurality of n bits, where n is a positive integer value and wherein each processing element of an enabled portion of the plurality of processing elements provides a first portion of a data value stored therein to a comparison line, the first portion of each of the plurality of data values being a most significant bit of the data value; iv) providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state; v) providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state; vi) selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements; vii) accessing a next one of the plurality of bits of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted; viii) providing the next one of the plurality of bits of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line; ix) providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the first logic state; providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the second logic state; xi) negating one of the plurality of enable values when the next one of the plurality of bits of the data value is in a different logic state than the comparison line; xii) repeating steps vii) through xi) for a predetermined number of repetitions; and xiii) inverting a portion of the plurality of bits of the data value provided by each of the plurality of processing elements before providing the portion of the plurality of bits to the comparison line, the portion of the plurality of bits not including the most significant bit of the data value.
Claim 62
Independent Claim
506 words
A method of comparing a plurality of data values in a data processor, comprising the steps of: i) receiving a comparison instruction; ii) decoding the comparison instruction to provide a plurality of control signals; iii) determining which of a plurality of processing elements are enabled, wherein each of the plurality of data values stored in each one of the plurality of processing elements has a plurality of n bits, where n is a positive integer value and wherein each processing element of an enabled portion of the plurality of processing elements provides a first portion of a data value stored therein to a comparison line, the first portion of each of the plurality of data values being a most significant bit of the data value; iv) providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state; v) providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state; vi) selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements; vii) accessing a next one of the plurality of bits of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted; viii) providing the next one of the plurality of bits of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line; ix) providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the first logic state; providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the second logic state; xi) negating one of the plurality of enable values when the next one of the plurality of bits of the data value is in a different logic state than the comparison line; xii) repeating steps vii) through xi) for a predetermined number of repetitions; and xiii) inverting a portion of the plurality of bits of the data value provided by each of the plurality of processing elements before providing the portion of the plurality of bits to the comparison line, the portion of the plurality of bits not including the most significant bit of the data value.
Claim 63
Dependent Claim
457 words
A data processing system, comprising: a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising: storage means for storing a comparison instruction; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state; each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors; a switch circuit which is coupled to the comparison conductor; a first integrated circuit pin; and a second integrated circuit pin, wherein the first integrated circuit pin of a first one of the plurality of data processors is coupled to a second integrated circuit pin of the second one of the plurality of data processors, the first integrated circuit pin coupling the comparison conductor to the second integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor, and wherein the first integrated circuit pin transfers control information when the first one of the plurality of data processors is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the first one of the plurality of data processors is in a second mode of operation.
Claim 64
Dependent Claim
457 words
A data processing system, comprising: a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising: storage means for storing a comparison instruction; an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction; instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals; a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction; a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state; each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors; a switch circuit which is coupled to the comparison conductor; a first integrated circuit pin; and a second integrated circuit pin, wherein the first integrated circuit pin of a first one of the plurality of data processors is coupled to a second integrated circuit pin of the second one of the plurality of data processors, the first integrated circuit pin coupling the comparison conductor to the second integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor, and wherein the first integrated circuit pin transfers control information when the first one of the plurality of data processors is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the first one of the plurality of data processors is in a second mode of operation.
References Cited (Backward Citations)
US3796992A
Cited
US4463445A
Cited
US4470112A
Cited
US4488218A
Cited
EP0112982A2
Cited
US4546428A
Cited
US5152000A
Cited
US5226171A
Cited
US4809169A
Cited
US4985832A
Cited
US5155389A
Cited
US5168573A
Cited
US5230057A
Cited
US5083285A
Cited
US5150328A
Cited
US5150327A
Cited
US5140530A
Cited
US5073867A
Cited
US5197030A
Cited
US5140523A
Cited
US5197130A
Cited
US5067095A
Cited
US5086405A
Cited
WO1991019259A1
Cited
US5208900A
Cited
US5216751A
Cited
US5175858A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |