US5168573A
Expired / Lapsed
US
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Memory device for storing vector registers
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-03-24
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Granted: 1992-12-01
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Expires: 2009-03-24
Abstract
Abstract A vector register provides the capability for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.
Inventors
- 👤 Tryggve Fossum
- 👤 Dwight P. Manley
- 👤 Francis X. McKeen
- 👤 Michael M. Tahranian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/3013; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
111 words
A memory device for storing data into and receiving data from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words, said memory device comprising: a second number of memory banks containing said words of said logical vector register circuit; and control means, coupled to said banks, for providing access to said words in said banks for storage and retrieval such that successive words in each of said register subarrays correspond to words in different ones of said memory banks, and such that successive words in each one of said memory banks correspond to words in different ones of said register subarrays.
Claim 2
Dependent Claim
111 words
A memory device for storing data into and receiving data from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words, said memory device comprising: a second number of memory banks containing said words of said logical vector register circuit; and control means, coupled to said banks, for providing access to said words in said banks for storage and retrieval such that successive words in each of said register subarrays correspond to words in different ones of said memory banks, and such that successive words in each one of said memory banks correspond to words in different ones of said register subarrays.
Claim 3
Dependent Claim
14 words
The memory device of claim 1 wherein said first and second numbers are equal.
Claim 4
Dependent Claim
37 words
The memory device of claim 1 wherein said memory banks are organized sequentially in a repeating order and wherein successive words of each of said register subarrays correspond to words in sequential ones of said memory banks.
Claim 5
Dependent Claim
39 words
The memory device of claim 1 wherein said register subarrays are accessed by a logical vector register address received from said logical vector register circuit, and wherein said control means includes counters loaded with said logical vector register address.
Claim 6
Dependent Claim
28 words
The memory device of claim 4 wherein said control means also includes conflict detection means to prevent multiple accesses to the same register subarray at the same time.
Claim 7
Dependent Claim
34 words
The memory device of claim 4 wherein said counters include first counters to select different ones of the memory banks, and second counters to select different ones of the words in said memory banks.
Claim 8
Dependent Claim
39 words
The memory device of claim 4 wherein said counters include read counters containing logical vector register addresses for reading data from said memory device, and write counters containing logic vector register addresses for writing data into said memory device.
Claim 9
Dependent Claim
56 words
The memory device of claim 4 wherein said logical vector register circuit performs addition and multiplication operations using said data in said memory device, and wherein said counters include addition counters containing the logical vector register addresses used for said addition operations, and multiplication counters containing the logical vector register addresses used for said multiplication operations.
Claim 10
Independent Claim
106 words
A method of accessing a memory device containing data organized as a first number of register subarrays each containing a plurality of words accessed by a logical vector register circuit, the method comprising the steps, performed by a memory device, of: storing said data into words in a plurality of memory banks of said memory device such that successive words in each of said register subarrays correspond to words in different ones of said memory banks; and storing said data into said words in said banks such that successive words in each one of said memory banks correspond to words in different ones of said subarrays.
Claim 11
Independent Claim
106 words
A method of accessing a memory device containing data organized as a first number of register subarrays each containing a plurality of words accessed by a logical vector register circuit, the method comprising the steps, performed by a memory device, of: storing said data into words in a plurality of memory banks of said memory device such that successive words in each of said register subarrays correspond to words in different ones of said memory banks; and storing said data into said words in said banks such that successive words in each one of said memory banks correspond to words in different ones of said subarrays.
Claim 12
Dependent Claim
48 words
The method of claim 9 wherein said step of storing successive words of each of said subarrays to correspond to words in different ones of said memory banks includes the substep of storing successive words of each of said register subarrays into sequential ones of said memory banks.
Claim 13
Dependent Claim
51 words
The method of claim 9 further including the step of forming logical vector register addresses for accessing said memory device, said logical vector register address forming step including the substeps of placing an initial logical vector address into a counter; and incrementing said counter to access successive one of said words.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |