Method of fabricating backside illuminated FET optical receiver with gallium arsenide species

Claim 1

A method of fabricating a light sensitive photo field effect transistor comprising the steps of: growing a plurality of layers on a surrogate first substrate member; forming a mesa on said surrogate first substrate member, wherein said mesa includes said plurality of layers; depositing ohmic contact metal on said mesa and on a portion of said surrogate first substrate member adjacent said mesa; forming a recessed area in said mesa to define a source, a drain, and a transistor active region; forming a Shottky barrier gate electrode within said recessed area between said source and said drain; forming a filler layer over said surrogate first substrate member adjacent said mesa, over the sidewalls of said mesa, and within said recessed area; forming an adhesive layer on said filler layer and on said ohmic contact metal located on the crown of said mesa; attaching a permanent second substrate member to said adhesive layer, said filler layer and said ohmic contact metal located on said crown of said mesa; removing said surrogate first substrate member and one of said plurality of layers to uncover a input light receptor planar backside surface area of said active region, and to expose the backside of said ohmic contact metal; located adjacent said mesa; forming electrical pads on a portion of said backside of said ohmic contact metal.

Claim 2

A method of fabricating a light sensitive photo field effect transistor comprising the steps of: growing a plurality of layers on a surrogate first substrate member; forming a mesa on said surrogate first substrate member, wherein said mesa includes said plurality of layers; depositing ohmic contact metal on said mesa and on a portion of said surrogate first substrate member adjacent said mesa; forming a recessed area in said mesa to define a source, a drain, and a transistor active region; forming a Shottky barrier gate electrode within said recessed area between said source and said drain; forming a filler layer over said surrogate first substrate member adjacent said mesa, over the sidewalls of said mesa, and within said recessed area; forming an adhesive layer on said filler layer and on said ohmic contact metal located on the crown of said mesa; attaching a permanent second substrate member to said adhesive layer, said filler layer and said ohmic contact metal located on said crown of said mesa; removing said surrogate first substrate member and one of said plurality of layers to uncover a input light receptor planar backside surface area of said active region, and to expose the backside of said ohmic contact metal; located adjacent said mesa; forming electrical pads on a portion of said backside of said ohmic contact metal.

Claim 20

The method of fabricating a light sensitive gallium arsenide photo field effect transistor comprising the steps of: growing three metal semiconductor field effect transistor (MESFET)-related, planar semiconductor layers on a single crystal gallium arsenide surrogate first substrate member, said semiconductor layers include an aluminum arsenide etch stop sacrificial first layer of 500 Angstroms thickness formed on said surrogate first substrate member, an n- gallium arsenide second layer of 1500 Angstroms thickness formed on said stop etch sacrificial first layer, and an n+ gallium arsenide third layer of 500 angstroms thickness formed on said second layer; forming a mesa on said surrogate first substrate member, wherein said mesa includes said semiconductor layers; depositing nickel-gold-germanium ohmic contact metal on said mesa and on a portion of said surrogate first substrate member adjacent said mesa; forming a recessed area in said mesa to form a source, a drain, and a transistor active region, said recessed area extending completely through said third semiconductor layer and partially through said second semiconductor layer to form a depression therein; forming a metallic Shottky barrier gate electrode within said recessed area on said second semiconductor layer depression and between said source and said drain, wherein said metallic Shottky barrier gate is formed from a material of the group consisting of titanium-gold and titanium-platinum-gold and aluminum; forming a filler layer over said surrogate first substrate member adjacent said mesa, over the sidewalls of said mesa, and within said recessed area; forming a heat conductive epoxy adhesive layer on said filler layer and on said ohmic contact metal located on the crown of said mesa; attaching a permanent second substrate member to said adhesive layer, to said filler layer and to said ohmic contact metal located on said crown of said mesa; removing said surrogate first substrate member using a lapping and polishing process followed by selective etching sequence, followed by removing said aluminum arsenide etch stop sacrificial first layer, using a dilute hydrofluoric acid etching process, to uncover a input light-receptor planar backside surface area of said active region, and to expose the backside of said ohmic contact metal located adjacent said mesa; forming electrical pads on a portion of said backside of said ohmic contact metal.

Claim 21

The method of fabricating a light sensitive gallium arsenide photo field effect transistor comprising the steps of: growing three metal semiconductor field effect transistor (MESFET)-related, planar semiconductor layers on a single crystal gallium arsenide surrogate first substrate member, said semiconductor layers include an aluminum arsenide etch stop sacrificial first layer of 500 Angstroms thickness formed on said surrogate first substrate member, an n- gallium arsenide second layer of 1500 Angstroms thickness formed on said stop etch sacrificial first layer, and an n+ gallium arsenide third layer of 500 angstroms thickness formed on said second layer; forming a mesa on said surrogate first substrate member, wherein said mesa includes said semiconductor layers; depositing nickel-gold-germanium ohmic contact metal on said mesa and on a portion of said surrogate first substrate member adjacent said mesa; forming a recessed area in said mesa to form a source, a drain, and a transistor active region, said recessed area extending completely through said third semiconductor layer and partially through said second semiconductor layer to form a depression therein; forming a metallic Shottky barrier gate electrode within said recessed area on said second semiconductor layer depression and between said source and said drain, wherein said metallic Shottky barrier gate is formed from a material of the group consisting of titanium-gold and titanium-platinum-gold and aluminum; forming a filler layer over said surrogate first substrate member adjacent said mesa, over the sidewalls of said mesa, and within said recessed area; forming a heat conductive epoxy adhesive layer on said filler layer and on said ohmic contact metal located on the crown of said mesa; attaching a permanent second substrate member to said adhesive layer, to said filler layer and to said ohmic contact metal located on said crown of said mesa; removing said surrogate first substrate member using a lapping and polishing process followed by selective etching sequence, followed by removing said aluminum arsenide etch stop sacrificial first layer, using a dilute hydrofluoric acid etching process, to uncover a input light-receptor planar backside surface area of said active region, and to expose the backside of said ohmic contact metal located adjacent said mesa; forming electrical pads on a portion of said backside of said ohmic contact metal.