Patent US5659697A successfully refreshed from Google Patents.
US5659697A
Expired / Lapsed
US
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Translation lookaside buffer for faster processing in response to availability of a first virtual address portion before a second virtual address portion
Assignee: International Business Machines Corp
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Filing: 1994-12-14
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Granted: 1997-08-19
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Expires: 2014-12-14
Abstract
Abstract A processing system and method of operation are provided. First translation information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first translation information and a first portion of a first address. Second translation information is stored. A logic state of a second match line is selectively modified in response to a comparison between the second translation information and a second portion of the first address. The logic state of the second match line is selectively modified in response to the logic state of the first match line. A second address is selectively output in response to the logic state of the second match line.
Inventors
- 👤 Carl Dean Dietz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:21
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
120 words
A processing system, comprising: first circuitry for storing first translation information and selectively modifying a logic state of a first match line in response to a comparison between said first translation information and a first portion of a first address; second circuitry for storing second translation information and selectively modifying a logic state of a second match line in response to a comparison between said second translation information and a second portion of said first address; third circuitry for selectively modifying said logic state of said second match line in response to said logic state of said first match line; and fourth circuitry for selectively outputting a second address in response to said logic state of said second match line.
Claim 2
Dependent Claim
120 words
A processing system, comprising: first circuitry for storing first translation information and selectively modifying a logic state of a first match line in response to a comparison between said first translation information and a first portion of a first address; second circuitry for storing second translation information and selectively modifying a logic state of a second match line in response to a comparison between said second translation information and a second portion of said first address; third circuitry for selectively modifying said logic state of said second match line in response to said logic state of said first match line; and fourth circuitry for selectively outputting a second address in response to said logic state of said second match line.
Claim 3
Dependent Claim
26 words
The system of claim 1 wherein said first portion of said first address is available for said comparison before said second portion of said first address.
Claim 4
Dependent Claim
29 words
The system of claim 1 and further comprising a translation unit for translating at least a portion of an effective address into said second portion of said first address.
Claim 5
Dependent Claim
36 words
The system of claim 3 wherein said second portion of said first address is available from said translation unit, and wherein said first portion of said first address is available from said effective address without translation.
Claim 6
Dependent Claim
13 words
The system of claim 1 wherein said first address is a virtual address.
Claim 7
Dependent Claim
13 words
The system of claim 5 wherein said second address is a real address.
Claim 8
Dependent Claim
15 words
The system of claim 6 wherein said real address is associated with said virtual address.
Claim 9
Dependent Claim
18 words
The system of claim 1 wherein a translation lookaside buffer includes said first, second, third and fourth circuitry.
Claim 10
Dependent Claim
15 words
The system of claim 1 wherein said first and second circuitry are identical in design.
Claim 11
Dependent Claim
13 words
The system of claim 9 wherein said first and second circuitry are cascadable.
Claim 12
Dependent Claim
17 words
The system of claim 10 wherein said first and second circuitry are coupled together in a sequence.
Claim 13
Independent Claim
115 words
A method of operating a processing system, comprising the steps of: storing first translation information and selectively modifying a logic state of a first match line in response to a comparison between said first translation information and a first portion of a first address; storing second translation information and selectively modifying a logic state of a second match line in response to a comparison between said second translation information and a second portion of said first address; selectively modifying said logic state of said second match line in response to said logic state of said first match line; and selectively outputting a second address in response to said logic state of said second match line.
Claim 14
Independent Claim
115 words
A method of operating a processing system, comprising the steps of: storing first translation information and selectively modifying a logic state of a first match line in response to a comparison between said first translation information and a first portion of a first address; storing second translation information and selectively modifying a logic state of a second match line in response to a comparison between said second translation information and a second portion of said first address; selectively modifying said logic state of said second match line in response to said logic state of said first match line; and selectively outputting a second address in response to said logic state of said second match line.
Claim 15
Dependent Claim
26 words
The method of claim 12 wherein said first portion of said first address is available for said comparison before said second portion of said first address.
Claim 16
Dependent Claim
28 words
The method of claim 12 and further comprising the step of translating at least a portion of an effective address into said second portion of said first address.
Claim 17
Dependent Claim
35 words
The method of claim 14 wherein said second portion of said first address is available from said translating, and wherein said first portion of said first address is available from said effective address without translation.
Claim 18
Dependent Claim
13 words
The method of claim 12 wherein said first address is a virtual address.
Claim 19
Dependent Claim
13 words
The method of claim 16 wherein said second address is a real address.
Claim 20
Dependent Claim
15 words
The method of claim 17 wherein said real address is associated with said virtual address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-18 | 2001-02-17 | 2001-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-18 | 2005-02-17 | 2005-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-18 | 2009-02-17 | 2009-08-19 | $7700.00 | Window Closed / Lapsed |