Abstract A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.
A silicon-on-insulator substrate comprising: a silicon handle wafer having a thermally oxidized surface; and a chemically etched epitaxial single crystal silicon device layer having a first surface and a second surface, wherein: the first surface is parallel to the second surface; said epitaxial single crystal silicon device layer has a thickness between 0.01 micron and 2 microns; said epitaxial single crystal silicon device layer has the first surface situated on and bonded to the oxidized surface of said silicon handle wafer, the oxidized surface being a buried oxide layer between said silicon handle wafer and said epitaxial single crystal silicon device layer; said epitaxial single crystal silicon device layer has a thickness variation within plus and minus 50 angstroms; and said buried oxide layer is free of pin holes.
Claim 2
Dependent Claim
129 words
A silicon-on-insulator substrate comprising: a silicon handle wafer having a thermally oxidized surface; and a chemically etched epitaxial single crystal silicon device layer having a first surface and a second surface, wherein: the first surface is parallel to the second surface; said epitaxial single crystal silicon device layer has a thickness between 0.01 micron and 2 microns; said epitaxial single crystal silicon device layer has the first surface situated on and bonded to the oxidized surface of said silicon handle wafer, the oxidized surface being a buried oxide layer between said silicon handle wafer and said epitaxial single crystal silicon device layer; said epitaxial single crystal silicon device layer has a thickness variation within plus and minus 50 angstroms; and said buried oxide layer is free of pin holes.
Claim 3
Dependent Claim
24 words
The substrate of claim 1 wherein said epitaxial single crystal silicon device layer has a boron concentration less than 10 15 /cm 3 .
Claim 4
Dependent Claim
24 words
The substrate of claim 1 wherein said epitaxial single crystal silicon device layer has a boron concentration less than 10 17 /cm 3 .
Claim 5
Dependent Claim
23 words
The silicon-on-insulator substrate of claim 1 wherein said buried oxide layer has fixed charge concentration of less than 5×10 10 /Cm 2 .
Claim 6
Dependent Claim
26 words
The silicon-on-insulator substrate of claim 1 wherein said epitaxial single crystal silicon device layer has a dislocation density of less than 10 2 /Cm 2 .