Systems and methods for implementing inter-device cell replacements

Claim 2

A memory system comprising: a first memory unit having an array of memory cells; a second memory unit having an array of memory cells including a number of redundant cells; an address bus; and a crossbar switch operable to switch an address addressing a defective cell in said array of said first memory unit and presented on said address bus to said second memory unit to access a selected one of said redundant cells.

Claim 3

The memory system of claim 1 wherein said crossbar switch is further operable to modify said address to generate a new address for switching to said second memory unit to accessing said selected one of said memory cells.

Claim 4

The memory system of claim 1 wherein said arrays comprise arrays of random access memory cells.

Claim 5

The memory system of claim 1 wherein said arrays comprise arrays of read-only memory cells.

Claim 6

The memory system of claim 1 wherein said memory units comprise dynamic random access memories packaged as single in line memory modules.

Claim 7

The memory system of claim 1 wherein said crossbar switch is further operable to switch a chip select signal from said first memory unit to said second memory unit.

Claim 8

A memory comprising: a first array of memory cells accessible by a set of addresses; a second array of memory cells including a first number of cells addressable by a first set of addresses and a second number of cells addressable by a second set of addresses; an address bus for carrying addresses; and a programmable crossbar switch operable to convert an address received from said address bus and addressing defective ones of said cells in said first array to a selected one of said second set of addresses and switch said selected one of said second set of addresses to access said second array.

Claim 9

A memory comprising: a first array of memory cells accessible by a set of addresses; a second array of memory cells including a first number of cells addressable by a first set of addresses and a second number of cells addressable by a second set of addresses; an address bus for carrying addresses; and a programmable crossbar switch operable to convert an address received from said address bus and addressing defective ones of said cells in said first array to a selected one of said second set of addresses and switch said selected one of said second set of addresses to access said second array.

Claim 10

The memory system of claim 7 wherein said second number of cells in said second array comprise redundant cells.

Claim 11

The memory system of claim 8 wherein said second number of cells in said second array comprise redundant rows of memory cells.

Claim 12

The memory system of claim 8 wherein said second number of cells in said second array comprise redundant columns of memory cells.

Claim 13

The memory system of claim 7 wherein said crossbar is further operable to switch a chip select signal from said first memory to said second memory.

Claim 14

The memory system of claim 7 wherein said first and second arrays are fabricated on separate integrated circuit chips.

Claim 15

The memory system of claim 12 wherein said separate chips are disposed in separate packages.

Claim 16

The memory system of claim 7 wherein said set of addresses for addressing said first array is the same as said first set of addresses addressing said first number of cells in said second array.

Claim 17

A memory system comprising: a plurality of memory units each including an array of rows and columns of primary memory cells addressable by a first set of addresses and a selected number of rows and columns of redundant memory cells addressable by a second set of addresses; an address bus; and a programable crossbar switch for coupling addresses from said address bus to a selected one of said memory units, said crossbar switch receiving a first address in said first set of addresses and addressing a defective cell in said array of a first one of said units and converting said address to a second address in said second set of addresses and switching said second address to a second one of said memory units.

Claim 18

A memory system comprising: a plurality of memory units each including an array of rows and columns of primary memory cells addressable by a first set of addresses and a selected number of rows and columns of redundant memory cells addressable by a second set of addresses; an address bus; and a programable crossbar switch for coupling addresses from said address bus to a selected one of said memory units, said crossbar switch receiving a first address in said first set of addresses and addressing a defective cell in said array of a first one of said units and converting said address to a second address in said second set of addresses and switching said second address to a second one of said memory units.

Claim 19

The memory system of claim 15 wherein said programmable crossbar switch is further operable to present an active chip select signal to said second one of said memory units to select said second memory unit for accessing.

Claim 20

The memory system of claim 15 and further comprising memory control circuitry for providing timing and control signals for operating said second memory unit in an active cycle.

Claim 21

The memory system of claim 17 wherein said memory control circuitry comprises core logic.

Claim 22

The memory system of claim 17 wherein said memory control circuitry comprises a memory controller.

Claim 23

The memory system of claim 17 wherein said memory units comprise discrete dynamic random access memory devices.

Claim 24

The memory system of claim 17 wherein said memory units dynamic random access memory single in line memory modules.

Claim 27

The method of claim 22 and further comprising the step of replacing at least one other defective group of cells within the first array with operational cells within the first array.

Claim 28

The method of claim 22 and further comprising the step of replacing a defective group of cells within the second memory cell array with operational cells within the first cell array.

Claim 29

The method of claim 22 wherein said step of converting includes the substep of modifying at least one least significant bit of the received address.