US5485424A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory and redundant-address writing method
Assignee: Fujitsu Ltd
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Filing: 1993-12-23
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Granted: 1996-01-16
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Expires: 2013-12-23
Abstract
Abstract The objects of the present invention are to enhance the operating speed by improving the access speed to a redundant memory, and also to enable a redundant address to be written into an electrically programmable memory device, which stores the redundant address, even for a semiconductor memory designed to operate with a low-voltage, single power supply. In a semiconductor memory according to a first aspect of the invention, an address detection circuit, which determines whether the access is for a replaced element, is constructed with a gate circuit that can be set either to such a state as to enable one of two complementary input signals for output or to a high impedance state, and a signal line, onto which a signal to inhibit the selection of normal memory cells is output upon detection of an address signal for redundancy, is directly controlled by an output of a redundancy memory circuit which stores the state of the redundancy function. Furthermore, in a semiconductor memory according to a second aspect of the invention, the write voltage for writing an address into a redundancy nonvolatile semiconductor memory is supplied from outside the semiconductor memory.
Inventors
- 👤 Shouichi Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:36
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
250 words
A semiconductor memory comprising: a matrix array of normal memory cells; a decoder for selecting some of said memory cells in accordance with an address signal; redundant cells for replacing some of said memory cells; and a redundancy decision circuit for detecting whether the address signal is a signal that selects a part replaced by said redundant cells, and for disabling selection by said decoder and enabling selection of said redundant cells when the signal is for the replaced part, said redundancy decision circuit including: gate circuits that can be set either to such a state as to enable one of the complementary input signals for output, or to a high impedance state; a redundant-address memory, constructed of a nonvolatile semiconductor memory, for outputting a signal that sets the state of said gates; a redundancy decoder which, when the outputs of said gate circuits are put in a prescribed state, outputs a signal to select said redundant cell and, at the same time, outputs a select-inhibit signal onto a redundancy select signal line to said decoder to inhibit the selection of any of said memory cells; a redundancy setting memory for storing information regarding whether redundancy is switched on or not; and a select line setting circuit which outputs a signal onto said redundancy select signal line not to inhibit the selection when redundancy is not switched on, and which is put in a high impedance state with respect to said redundancy select signal line when redundancy is switched on.
Claim 2
Dependent Claim
250 words
A semiconductor memory comprising: a matrix array of normal memory cells; a decoder for selecting some of said memory cells in accordance with an address signal; redundant cells for replacing some of said memory cells; and a redundancy decision circuit for detecting whether the address signal is a signal that selects a part replaced by said redundant cells, and for disabling selection by said decoder and enabling selection of said redundant cells when the signal is for the replaced part, said redundancy decision circuit including: gate circuits that can be set either to such a state as to enable one of the complementary input signals for output, or to a high impedance state; a redundant-address memory, constructed of a nonvolatile semiconductor memory, for outputting a signal that sets the state of said gates; a redundancy decoder which, when the outputs of said gate circuits are put in a prescribed state, outputs a signal to select said redundant cell and, at the same time, outputs a select-inhibit signal onto a redundancy select signal line to said decoder to inhibit the selection of any of said memory cells; a redundancy setting memory for storing information regarding whether redundancy is switched on or not; and a select line setting circuit which outputs a signal onto said redundancy select signal line not to inhibit the selection when redundancy is not switched on, and which is put in a high impedance state with respect to said redundancy select signal line when redundancy is switched on.
Claim 3
Dependent Claim
19 words
A semiconductor memory according to claim 1, wherein said normal memory cells are electrically programmable nonvolatile semiconductor memory cells.
Claim 4
Dependent Claim
52 words
A semiconductor memory according to claim 1, wherein said gate circuits are each constructed with a plurality of circuits having two buffer gates to which normal and complement signals of each bit in the address signal are respectively input, and whose outputs are capable of being put in a high impedance state.
Claim 5
Dependent Claim
52 words
A semiconductor memory according to claim 2, wherein said gate circuits are each constructed with a plurality of circuits having two buffer gates to which normal and complement signals of each bit in the address signal are respectively input, and whose outputs are capable of being put in a high impedance state.
Claim 6
Dependent Claim
125 words
A semiconductor memory comprising: a matrix array of normal memory cells; a decoder for selecting part of said memory cells in accordance with an address signal; a redundant cell for replacing some of said memory cells; and a redundancy decision circuit for detecting whether the address signal is a signal that selects a part replaced by said redundant cells, and for disabling selection by said decoder and enabling selection of said redundant cells when the signal is for the replaced part, said redundancy decision circuit including an electrically programmable nonvolatile semiconductor redundancy memory for storing the address of the part replaced by said redundant cells, a write voltage for writing the address into said redundancy nonvolatile semiconductor memory being supplied from outside said semiconductor memory.
Claim 7
Dependent Claim
125 words
A semiconductor memory comprising: a matrix array of normal memory cells; a decoder for selecting part of said memory cells in accordance with an address signal; a redundant cell for replacing some of said memory cells; and a redundancy decision circuit for detecting whether the address signal is a signal that selects a part replaced by said redundant cells, and for disabling selection by said decoder and enabling selection of said redundant cells when the signal is for the replaced part, said redundancy decision circuit including an electrically programmable nonvolatile semiconductor redundancy memory for storing the address of the part replaced by said redundant cells, a write voltage for writing the address into said redundancy nonvolatile semiconductor memory being supplied from outside said semiconductor memory.
Claim 8
Dependent Claim
40 words
A semiconductor memory according to claim 5, further including a special electrode pad to which the write voltage for writing the address into said redundancy nonvolatile semiconductor memory is applied, and which is not used in a final assembled product.
Claim 9
Dependent Claim
67 words
A semiconductor memory comprising a redundant cell for replacing a part of normal memory cells arranged in a matrix array, and an electrically programmable redundancy nonvolatile semiconductor memory for storing the address of the part to be replaced, further comprising means for dividing a redundant address into a plurality of bits, and for writing said plurality of bits into said redundancy nonvolatile semiconductor memory by time division.
Claim 10
Dependent Claim
67 words
A semiconductor memory comprising a redundant cell for replacing a part of normal memory cells arranged in a matrix array, and an electrically programmable redundancy nonvolatile semiconductor memory for storing the address of the part to be replaced, further comprising means for dividing a redundant address into a plurality of bits, and for writing said plurality of bits into said redundancy nonvolatile semiconductor memory by time division.
Claim 11
Dependent Claim
96 words
In a semiconductor memory comprising a redundant cell for replacing a part of normal memory cells arranged in a matrix array, and an electrically programmable redundancy nonvolatile semiconductor memory for storing an address of the part to be replaced, a redundant-address writing method for writing the address of the part to be replaced into said redundancy nonvolatile semiconductor memory, said method comprising the steps of: dividing the address of the part to be replaced into a plurality of bits; and writing said plurality of bits into the electrically programmable redundancy nonvolatile semiconductor memory by time division.
Claim 12
Dependent Claim
96 words
In a semiconductor memory comprising a redundant cell for replacing a part of normal memory cells arranged in a matrix array, and an electrically programmable redundancy nonvolatile semiconductor memory for storing an address of the part to be replaced, a redundant-address writing method for writing the address of the part to be replaced into said redundancy nonvolatile semiconductor memory, said method comprising the steps of: dividing the address of the part to be replaced into a plurality of bits; and writing said plurality of bits into the electrically programmable redundancy nonvolatile semiconductor memory by time division.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |