US5656961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency clock signal distribution with high voltage output
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-12
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Granted: 1997-08-12
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Expires: 2013-10-12
Abstract
Abstract A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
Inventors
- 👤 Thanh Thien Tran
- 👤 Clarence Y. Mar
- 👤 Javier F. Izquierdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:16
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
A method for distributing a clock signal having a frequency greater than or equal to 50 MHz in a digital computer system to an element which uses a square wave clock signal provided to a clock signal input, comprising the steps of: developing a sine wave signal having the frequency of the desired clock signal; conducting said sine wave signal across a connector to a location near the element which uses the square wave clock signal; converting said conducted sine wave signal into a square wave signal having the same frequency as the sine wave signal; and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal.
Claim 2
Independent Claim
117 words
A method for distributing a clock signal having a frequency greater than or equal to 50 MHz in a digital computer system to an element which uses a square wave clock signal provided to a clock signal input, comprising the steps of: developing a sine wave signal having the frequency of the desired clock signal; conducting said sine wave signal across a connector to a location near the element which uses the square wave clock signal; converting said conducted sine wave signal into a square wave signal having the same frequency as the sine wave signal; and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal.
Claim 3
Dependent Claim
29 words
The method of claim 1, further comprising: removing any direct current level from said conducted sine wave signal before converting said sine wave signal to a square wave signal.
Claim 4
Dependent Claim
91 words
The method of claim 1, the digital computer system including a plurality of elements which use a square wave clock signal provided to a clock signal input, wherein said steps of converting said conducted sine wave signal into said square wave signal and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal are repeated for each of the plurality of elements which use the square wave signal, whereby each of the plurality of elements receives a repeated square wave signal.
Claim 5
Dependent Claim
139 words
A digital logic system with a clock signal having a frequency greater than or equal to 50 MHz, comprising: first circuitry having a square wave clock signal input for receiving a square wave signal of a desired frequency, said desired frequency being greater than or equal to 50 MHz; means for developing and outputting a sine wave signal having a frequency of the desired square wave signal frequency; means for conducting said sine wave signal across a connector to a location near said first circuitry; means for receiving said conducted sine wave signal and for converting said conducted sine wave signal into a square wave signal having the same frequency as said sine wave signal and outputting said square wave signal; and means for conducting said output square wave signal to said first circuitry square wave clock signal input.
Claim 6
Dependent Claim
139 words
A digital logic system with a clock signal having a frequency greater than or equal to 50 MHz, comprising: first circuitry having a square wave clock signal input for receiving a square wave signal of a desired frequency, said desired frequency being greater than or equal to 50 MHz; means for developing and outputting a sine wave signal having a frequency of the desired square wave signal frequency; means for conducting said sine wave signal across a connector to a location near said first circuitry; means for receiving said conducted sine wave signal and for converting said conducted sine wave signal into a square wave signal having the same frequency as said sine wave signal and outputting said square wave signal; and means for conducting said output square wave signal to said first circuitry square wave clock signal input.
Claim 7
Dependent Claim
44 words
The digital logic system of claim 4, wherein said means for receiving said conducted sine wave signal and for converting said conducted sine wave signal includes means for removing direct current components from said sine wave signal prior to converting said sine wave signal.
Claim 8
Dependent Claim
98 words
The digital logic system of claim 4 further comprising: second circuitry having a square wave clock signal input for receiving a square wave signal of said desired frequency; means for conducting said sine wave signal to a location near said second circuitry; means for receiving said conducted sine wave signal and for converting said conducted sine wave signal into a second square wave signal having the same frequency as said sine wave signal and outputting said second square signal; and means for conducting said second output square wave signal to said second circuitry square wave clock signal input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |