US5656822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin film transistor having increased effective channel width
Assignee: Nokia of America Corp
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Filing: 1995-08-28
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Granted: 1997-08-12
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Expires: 2015-08-28
Abstract
Abstract The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chun-Ting Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
74 words
A thin film transistor, comprising: a substrate, a polysilicon gate electrode layer including first longitudinal edges overlying said substrate, and an amorphous silicon layer including an undoped control channel area having second longitudinal edges overlying said gate electrode layer, the first longitudinal edges of said gate electrode layer being in substantial alignment with the second longitudinal edges of the undoped control channel area, thereby increasing an effective channel width of the thin film transistor.
Claim 2
Dependent Claim
74 words
A thin film transistor, comprising: a substrate, a polysilicon gate electrode layer including first longitudinal edges overlying said substrate, and an amorphous silicon layer including an undoped control channel area having second longitudinal edges overlying said gate electrode layer, the first longitudinal edges of said gate electrode layer being in substantial alignment with the second longitudinal edges of the undoped control channel area, thereby increasing an effective channel width of the thin film transistor.
Claim 3
Dependent Claim
25 words
The thin-film transistor of claim 1, in which said amorphous silicon layer includes opposing ends which are doped to form spaced source and drain regions.
References Cited (Backward Citations)
US4720736A
Cited
JPS62120076A
Cited
US5202572A
Cited
US5115289A
Cited
JPH02260460A
Cited
US5283455A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |