Method of manufacturing high aspect-ratio field emitters for flat panel displays

Claim 1

A method for fabricating an array of gated field emitter structures having high aspect ratios on an insulating substrate comprising the steps of: providing an insulating substrate; depositing a first electrically conducting layer on said insulating substrate; patterning said first electrically conducting layer by photoresist masking and etching and thereby forming cathodes comprising of an array of parallel first conducting strips in a first direction on said substrate; depositing a blanket insulating layer on said first conducting strips and elsewhere on said substrate; depositing a second electrically conducting layer on said insulating layer; patterning said second electrically conducting layer by photoresist masking and etching and thereby forming a gate electrode comprising of an array of parallel second conducting strips in a second direction that cross over said array of parallel first conducting strips; forming openings in said second conducting strips to said insulating layer over portions of said first conducting strips by photoresist masking and etching; and etching said insulating layer in said openings to said first conducting strips and recessing the sidewalls of said insulating layer in said openings and under said second conducting strips; removing said photoresist mask; depositing a release layer at a shallow angle on said insulating substrate while rotating said substrate about an axis normal to said substrate surface, and thereby forming said release layer on said substrate surface and on sidewalls of said openings in said second conducting strips; heating said insulating substrate in an evacuated evaporation system prior to depositing a third conducting layer for the purpose of forming said electron field emitter structures having high aspect ratios; depositing a third conducting layer at normal incidence on said heated substrate surface, and thereby forming in said openings on said first conducting strips said array of high aspect ratio gated field emitter structures and said third conducting layer deposited elsewhere on said substrate and physically separated from said array of field emitter structures; etching said release layer and lifting off said third conducting layer elsewhere on said substrate, and thereby completing said array of high aspect ratio gate field emitter structures on said array of cathode electrodes, and furthermore having an array of gate electrodes with openings that are self-aligned, coplanar and in close proximity to the tips of said gated field emitters.

Claim 2

A method for fabricating an array of gated field emitter structures having high aspect ratios on an insulating substrate comprising the steps of: providing an insulating substrate; depositing a first electrically conducting layer on said insulating substrate; patterning said first electrically conducting layer by photoresist masking and etching and thereby forming cathodes comprising of an array of parallel first conducting strips in a first direction on said substrate; depositing a blanket insulating layer on said first conducting strips and elsewhere on said substrate; depositing a second electrically conducting layer on said insulating layer; patterning said second electrically conducting layer by photoresist masking and etching and thereby forming a gate electrode comprising of an array of parallel second conducting strips in a second direction that cross over said array of parallel first conducting strips; forming openings in said second conducting strips to said insulating layer over portions of said first conducting strips by photoresist masking and etching; and etching said insulating layer in said openings to said first conducting strips and recessing the sidewalls of said insulating layer in said openings and under said second conducting strips; removing said photoresist mask; depositing a release layer at a shallow angle on said insulating substrate while rotating said substrate about an axis normal to said substrate surface, and thereby forming said release layer on said substrate surface and on sidewalls of said openings in said second conducting strips; heating said insulating substrate in an evacuated evaporation system prior to depositing a third conducting layer for the purpose of forming said electron field emitter structures having high aspect ratios; depositing a third conducting layer at normal incidence on said heated substrate surface, and thereby forming in said openings on said first conducting strips said array of high aspect ratio gated field emitter structures and said third conducting layer deposited elsewhere on said substrate and physically separated from said array of field emitter structures; etching said release layer and lifting off said third conducting layer elsewhere on said substrate, and thereby completing said array of high aspect ratio gate field emitter structures on said array of cathode electrodes, and furthermore having an array of gate electrodes with openings that are self-aligned, coplanar and in close proximity to the tips of said gated field emitters.

Claim 14

A method for fabricating an array of gated field emitter structures having high aspect ratios and pedestals on an insulating substrate comprising the steps of: providing an insulating substrate; depositing a first electrically conducting layer on said insulating substrate; patterning said first electrically conducting layer by photoresist masking and etching and thereby forming cathodes comprising of an array of parallel first conducting strips in a first direction on said substrate; depositing a blanket insulating layer on said first conducting strips and elsewhere on said substrate; depositing a second electrically conducting layer on said insulating layer; patterning said second electrically conducting layer by photoresist masking and etching and thereby forming a gate electrode comprising of an array of parallel second conducting strips in a second direction that cross over said array of parallel first conducting strips; forming openings in said second conducting strips to said insulating layer over portions of said first conducting strips by photoresist masking and etching; and etching said insulating layer in said openings to said first conducting strips and recessing the sidewalls of said insulating layer in said openings and under said second conducting strips; removing said photoresist mask; depositing a release layer at a shallow angle on said insulating substrate while rotating said substrate about an axis normal to said substrate surface, and thereby forming said release layer on said substrate surface and on sidewalls of said openings in said second conducting strips; heating said insulating substrate in an evacuated evaporation system prior to depositing a first and second conducting pedestal layer and a third conducting layer for the purpose of forming said electron field emitter structures having high aspect ratios on said pedestal structure; depositing on said substrate said first conducting pedestal layer at normal incidence to said substrate surface; depositing on said substrate said second conducting pedestal layer at an angle to said substrate surface while rotating said substrate about an axis to said substrate surface; depositing a third conducting layer at normal incidence on said heated substrate surface, and thereby forming in said openings on said second conducting pedestal layer said array of high aspect ratio gated field emitter structures and said first and second pedestal and third conducting layer deposited elsewhere on said substrate are physically separated from said array of pedestals with field emitter structures thereon; etching said release layer and lifting off said first and second pedestal layer and said third conducting layer elsewhere on said substrate, and thereby completing said array of high aspect ratio gated field emitter structures having conducting pedestals on said array of cathode electrodes, and furthermore having an array of gate electrodes with openings that are self-aligned, coplanar and in close proximity to the tips of said high aspect-ratio gated field emitters.

Claim 15

A method for fabricating an array of gated field emitter structures having high aspect ratios and pedestals on an insulating substrate comprising the steps of: providing an insulating substrate; depositing a first electrically conducting layer on said insulating substrate; patterning said first electrically conducting layer by photoresist masking and etching and thereby forming cathodes comprising of an array of parallel first conducting strips in a first direction on said substrate; depositing a blanket insulating layer on said first conducting strips and elsewhere on said substrate; depositing a second electrically conducting layer on said insulating layer; patterning said second electrically conducting layer by photoresist masking and etching and thereby forming a gate electrode comprising of an array of parallel second conducting strips in a second direction that cross over said array of parallel first conducting strips; forming openings in said second conducting strips to said insulating layer over portions of said first conducting strips by photoresist masking and etching; and etching said insulating layer in said openings to said first conducting strips and recessing the sidewalls of said insulating layer in said openings and under said second conducting strips; removing said photoresist mask; depositing a release layer at a shallow angle on said insulating substrate while rotating said substrate about an axis normal to said substrate surface, and thereby forming said release layer on said substrate surface and on sidewalls of said openings in said second conducting strips; heating said insulating substrate in an evacuated evaporation system prior to depositing a first and second conducting pedestal layer and a third conducting layer for the purpose of forming said electron field emitter structures having high aspect ratios on said pedestal structure; depositing on said substrate said first conducting pedestal layer at normal incidence to said substrate surface; depositing on said substrate said second conducting pedestal layer at an angle to said substrate surface while rotating said substrate about an axis to said substrate surface; depositing a third conducting layer at normal incidence on said heated substrate surface, and thereby forming in said openings on said second conducting pedestal layer said array of high aspect ratio gated field emitter structures and said first and second pedestal and third conducting layer deposited elsewhere on said substrate are physically separated from said array of pedestals with field emitter structures thereon; etching said release layer and lifting off said first and second pedestal layer and said third conducting layer elsewhere on said substrate, and thereby completing said array of high aspect ratio gated field emitter structures having conducting pedestals on said array of cathode electrodes, and furthermore having an array of gate electrodes with openings that are self-aligned, coplanar and in close proximity to the tips of said high aspect-ratio gated field emitters.