US5656520A
Expired / Lapsed
US
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Semiconductor device and method of manufacturing the same
Assignee: NEC Electronics Corp
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Filing: 1996-05-22
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Granted: 1997-08-12
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Expires: 2016-05-22
Abstract
Abstract A semiconductor device and method for manufacturing same are provided. The method according to the present invention begins by sequentially forming in an element region of a semiconductor substrate a gate insulating film, a gate electrode, and a stopper film. An insulating interlayer is formed on the semiconductor substrate and is subsequently etched to remove it from the element region. An impurity is doped into the semiconductor substrate surrounded by the gate electrode and the insulating interlayer to form lightly doped diffusion layers. A sidewall spacer is formed on the sidewalls of the gate electrode and the insulating interlayer. An impurity is doped into the semiconductor substrate surrounded by the sidewall spacers to form heavily doped diffusion layers. Finally, electrode wiring is formed on the semiconductor device surrounded by the sidewall spacers.
Inventors
- 👤 Takeshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A method of manufacturing a semiconductor device, comprising: the steps of sequentially forming a gate insulating film, a gate electrode, and a stopper film in an element region on a semiconductor substrate; forming an insulating interlayer on said semiconductor substrate, and etching and removing said insulating interlayer in the element region; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer, and forming lightly doped diffusion layers; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer, and forming heavily doped diffusion layers; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed.
Claim 2
Independent Claim
143 words
A method of manufacturing a semiconductor device, comprising: the steps of sequentially forming a gate insulating film, a gate electrode, and a stopper film in an element region on a semiconductor substrate; forming an insulating interlayer on said semiconductor substrate, and etching and removing said insulating interlayer in the element region; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer, and forming lightly doped diffusion layers; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer, and forming heavily doped diffusion layers; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed.
Claim 3
Dependent Claim
49 words
A method according to claim 1, wherein in the step of forming said lightly doped diffusion layers, phosphorous and boron are alternately ion-implanted in different surfaces of said semiconductor device respectively at 40 KeV and about 1.5E13 cm -2 and at 15 KeV and about 1.5E13 cm -2 .
Claim 4
Dependent Claim
23 words
A method according to claim 2, wherein annealing is performed at 900° C. so as to activate said diffusion layers after ion implantation.
Claim 5
Dependent Claim
50 words
A method according to claim 1, wherein in the step of forming said heavily doped diffusion layers, arsenic and boron fluoride are alternately ion-implanted in different surfaces of said semiconductor device respectively at 70 KeV and about 5E15 cm -2 and at 30 KeV and about 5E15 cm -2 .
Claim 6
Dependent Claim
23 words
A method according to claim 4, wherein annealing is performed at 900° C. so as to activate said diffusion layers after ion implantation.
Claim 7
Independent Claim
148 words
A method of manufacturing a semiconductor device comprising: the steps in sequence of forming a gate insulating film, a gate electrode and a stopper film in an element region on a semiconductor substrate; forming an insulating interlayer on said semiconductor substrate, and etching and removing said insulating interlayer in the element region; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer, and forming lightly doped diffusion layers; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer, and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer; and wherein said stopper film comprises polysilicon, and said method further comprises the step of oxidizing the stopper film so as to integrate the stopper film into an oxide layer beneath said stopper film.
Claim 8
Independent Claim
148 words
A method of manufacturing a semiconductor device comprising: the steps in sequence of forming a gate insulating film, a gate electrode and a stopper film in an element region on a semiconductor substrate; forming an insulating interlayer on said semiconductor substrate, and etching and removing said insulating interlayer in the element region; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer, and forming lightly doped diffusion layers; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer, and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer; and wherein said stopper film comprises polysilicon, and said method further comprises the step of oxidizing the stopper film so as to integrate the stopper film into an oxide layer beneath said stopper film.
References Cited (Backward Citations)
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