Well resistor for ESD protection of CMOS circuits

Claim 2

An electrostatic discharge protection CMOS circuit formed on a single crystal semiconductor die having memory circuits formed therein, said circuit comprising: a pull up, N channel, field effect transistor having a gate for receiving an input signal, and a source and a drain; a pull down, N channel, field effect transistor having a gate for receiving the complement of the input signal, and a source and a drain; a first N-well resistor formed external to the transistors and coupled in series with the pull up transistor and a power supply line; a second N-well resistor formed external to the transistors and coupled in series with the pull down transistor and a ground line; and an output line coupled between the pull up and pull down transistors for providing an output signal representative of the input signal.

Claim 3

The circuit of claim 1 wherein the input signal comprises data from said memory circuits on the same die.

Claim 4

The circuit of claim 2 wherein the memory circuits are dynamic random access memory circuits.

Claim 5

The circuit of claim 1 wherein the sources and drains are formed of N+ doped silicon.

Claim 6

The circuit of claim 4 wherein the N-well resistor partially overlaps one of the N+ doped silicon source or drain so that the source or drain serves as a contact for one end of the resistor.

Claim 7

The circuit of claim 4 wherein the source and drains are covered with a conductive material to reduce their resistance and thereby increase the switching speed of the transistors.

Claim 8

The circuit of claim 6 wherein the conductive material is a silicide.

Claim 9

The circuit of claim 6 wherein the conductive material is tungsten silicide.

Claim 10

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; a first resistor formed external to the transistors and coupled in series with the pull up transistor and a power supply line; a second resistor formed external to the transistors and coupled in series with the pull down transistor and a ground line; and an output line coupled between the pull up and pull down transistors for providing an output signal representative of the input signal.

Claim 11

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; a first resistor formed external to the transistors and coupled in series with the pull up transistor and a power supply line; a second resistor formed external to the transistors and coupled in series with the pull down transistor and a ground line; and an output line coupled between the pull up and pull down transistors for providing an output signal representative of the input signal.

Claim 12

The circuit of claim 9 wherein the sources and drains are formed of N+doped silicon.

Claim 13

The circuit of claim 10 wherein the source and drains are covered with a conductive material to reduce their resistance and thereby increase the switching speed of the transistors.

Claim 14

The circuit of claim 10 wherein the conductive material is a silicide.

Claim 15

The circuit of claim 10 wherein the conductive material is tungsten silicide.

Claim 16

The circuit of claim 10 wherein the N-well resistor partially overlaps one of the N+ doped silicon source or drain so that the source or drain serves as a contact for one end of the resistor.

Claim 17

An electrostatic discharge protection CMOS circuit formed on a single crystal semiconductor die having DRAM memory circuits formed therein, said circuit comprising: a pull up, N channel, field effect transistor having a gate for receiving an input signal from the memory circuits, and a source and a drain; a pull down, N channel, field effect transistor having a gate for receiving the complement of the input signal, and a source and a drain; a first N-well resistor formed external to the transistors and coupled between a power supply line and the drain of the pull up transistor; a second N-well resistor formed external to the transistors and coupled between a ground line and the source of the pull down transistor; and an output line coupled between the source of the pull up transistor and the drain of the pull down transistor for providing an output signal representative of the input signal.

Claim 18

An electrostatic discharge protection CMOS circuit formed on a single crystal semiconductor die having DRAM memory circuits formed therein, said circuit comprising: a pull up, N channel, field effect transistor having a gate for receiving an input signal from the memory circuits, and a source and a drain; a pull down, N channel, field effect transistor having a gate for receiving the complement of the input signal, and a source and a drain; a first N-well resistor formed external to the transistors and coupled between a power supply line and the drain of the pull up transistor; a second N-well resistor formed external to the transistors and coupled between a ground line and the source of the pull down transistor; and an output line coupled between the source of the pull up transistor and the drain of the pull down transistor for providing an output signal representative of the input signal.

Claim 19

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain, said pull up and pull down transistors being coupled in series between a power supply line and a ground line; at a first resistor formed external to the transistors and coupled in series between the transistors; a second resistor formed external to the transistors and coupled in series with the first resistor between the transistors; and an output line coupled between the first and second resistors for providing an output signal representative of the input signal.

Claim 20

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain, said pull up and pull down transistors being coupled in series between a power supply line and a ground line; at a first resistor formed external to the transistors and coupled in series between the transistors; a second resistor formed external to the transistors and coupled in series with the first resistor between the transistors; and an output line coupled between the first and second resistors for providing an output signal representative of the input signal.

Claim 21

The circuit of claim 16 wherein the sources and drains are formed of N+ doped silicon.

Claim 22

The circuit of claim 17 wherein the N-well resistor partially overlaps one of the N+ doped silicon source or drain so that the source or drain serves as a contact for one end of the resistor.

Claim 23

The circuit of claim 17 wherein the source and drains are covered with a conductive material to reduce their resistance and thereby increase the switching speed of the transistors.

Claim 24

The circuit of claim 19 wherein the conductive material is a silicide.

Claim 25

The circuit of claim 19 wherein the conductive material is tungsten silicide.

Claim 26

An electrostatic discharge protection circuit formed between a power supply line and a ground line, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; an output line coupled between the pull up transistor and the pull down transistor; a first resistor formed external to the transistors and coupled in series with the pull up transistor between the power supply and the output line; and a second resistor formed external to the transistors and coupled in series with the pull down transistor between the ground line and the output line.

Claim 27

An electrostatic discharge protection circuit formed between a power supply line and a ground line, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; an output line coupled between the pull up transistor and the pull down transistor; a first resistor formed external to the transistors and coupled in series with the pull up transistor between the power supply and the output line; and a second resistor formed external to the transistors and coupled in series with the pull down transistor between the ground line and the output line.

Claim 28

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; an output line coupled between the pull up and pull down transistors for providing an output signal representative of the input signal; and said protection circuit further including at least one of: a first resistor formed external to the transistors and coupled in series with the pull up transistor and a power supply line; and a second resistor formed external to the transistors and coupled in series with the pull down transistor and a ground line.

Claim 29

An electrostatic discharge protection circuit, comprising: a pull up transistor having a gate for receiving an input signal, and a source and a drain; a pull down transistor having a gate for receiving the complement of the input signal, and a source and a drain; an output line coupled between the pull up and pull down transistors for providing an output signal representative of the input signal; and said protection circuit further including at least one of: a first resistor formed external to the transistors and coupled in series with the pull up transistor and a power supply line; and a second resistor formed external to the transistors and coupled in series with the pull down transistor and a ground line.

Claim 30

The circuit of claim 23 wherein the sources and drains are formed of N+ doped silicon.

Claim 31

The circuit of claim 24 wherein the first and second resistor comprise N-well resistors which partially overlap one of the N+ doped silicon source or drain of the respective pull up and pull down transistors so that the respective source and drain serve as a contact for one end of each resistor.

Claim 32

The circuit of claim 24 wherein the source and drains are covered with a conductive material to reduce their resistance and thereby increase the switching speed of the transistors.

Claim 33

The circuit of claim 26 wherein the conductive material is a silicide.

Claim 34

The circuit of claim 26 wherein the conductive material is tungsten silicide.