US5227327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits
Assignee: Seiko Epson Corp
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Filing: 1992-01-10
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Granted: 1993-07-13
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Expires: 2012-01-10
Abstract
Abstract An integrated circuit having MIS transistors pull-up and pull-down gate input resistors of a sufficient high resistance. The high resistance values are obtained in spite of using self-aligned refractory metal silicide films by redefining available channel stoppers to form the respective first terminals of the resistors and a contact region in a lightly doped substrate or well region to form the respective second terminals of the resistors.
Inventors
- 👤 Minoru Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:36
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
137 words
In a self-aligned I C manufacturing process that includes a self-aligned silicide process for depositing a layer of refractory metal silicide, a method for manufacturing a high impedance circuit for protecting inputs of metal-insulator-semiconductor (MIS) transistors, the method comprising the steps of: defining a body of a resistor to comprise a portion of a lightly doped volume of a semiconductor substrate, with the surface of the portion of the substrate uncovered by the layer of refractory metal silicide; defining a first terminal of the resistor to comprise a portion of a heavily doped channel stopper for coupling to a power supply potential; defining a second terminal of the resistor to comprise a heavily doped contact region within the substrate apart from the portion of the channel stopper for coupling to a gate input of a MIS transistor.
Claim 2
Dependent Claim
137 words
In a self-aligned I C manufacturing process that includes a self-aligned silicide process for depositing a layer of refractory metal silicide, a method for manufacturing a high impedance circuit for protecting inputs of metal-insulator-semiconductor (MIS) transistors, the method comprising the steps of: defining a body of a resistor to comprise a portion of a lightly doped volume of a semiconductor substrate, with the surface of the portion of the substrate uncovered by the layer of refractory metal silicide; defining a first terminal of the resistor to comprise a portion of a heavily doped channel stopper for coupling to a power supply potential; defining a second terminal of the resistor to comprise a heavily doped contact region within the substrate apart from the portion of the channel stopper for coupling to a gate input of a MIS transistor.
Claim 3
Dependent Claim
41 words
The method of claim 1, wherein the defining of the body of the resistor includes defining the body of the resistor to comprise a region of the lightly doped volume between the portion of the channel stopper and the contact region.
Claim 4
Dependent Claim
17 words
The method of claim 2, wherein the region of the lightly doped volume is an unbounded region.
Claim 5
Dependent Claim
21 words
The method of claim 3, wherein the defining of the second terminal includes defining the contact region on the substrate surface.
Claim 6
Dependent Claim
27 words
The method of claim 3, wherein the defining of the second terminal includes defining the contact region on the surface of a doped well in the substrate.
Claim 7
Dependent Claim
28 words
The method of claim 3, further comprising coupling of the first terminal to a positive power supply potential V dd so that the resistor constitutes a pull-up resistor.
Claim 8
Dependent Claim
28 words
The method of claim 3, further comprising coupling of the first terminal to a negative power supply potential V SS so that the resistor constitutes a pull-down resistor.
Claim 9
Dependent Claim
38 words
The method of claim 3, further comprising positioning the resistor and an associated MIS transistor to minimize the surface area of the substrate occupied, so that more circuits are fabricated on a given surface area of the substrate.
Claim 10
Dependent Claim
132 words
In a self-aligned IC manufacturing process that includes a self-aligned silicide process for depositing a layer of refractory metal silicide, a method for manufacturing a high impedance circuit for protecting active circuit components, the method comprising the steps of; defining a body of a resistor to comprise a portion of a lightly doped volume of a semiconductor substrate, with the surface of the portion of the substrate uncovered by the layer of refractory metal silicide; defining a first terminal of the resistor to comprise a portion of a heavily doped channel stopper for coupling to a power supply potential; and defining a second terminal of the resistor to comprise a heavily doped contact region within the substrate apart from the portion of the channel stopper for coupling to an active circuit component.
Claim 11
Dependent Claim
132 words
In a self-aligned IC manufacturing process that includes a self-aligned silicide process for depositing a layer of refractory metal silicide, a method for manufacturing a high impedance circuit for protecting active circuit components, the method comprising the steps of; defining a body of a resistor to comprise a portion of a lightly doped volume of a semiconductor substrate, with the surface of the portion of the substrate uncovered by the layer of refractory metal silicide; defining a first terminal of the resistor to comprise a portion of a heavily doped channel stopper for coupling to a power supply potential; and defining a second terminal of the resistor to comprise a heavily doped contact region within the substrate apart from the portion of the channel stopper for coupling to an active circuit component.
Claim 12
Dependent Claim
41 words
The method of claim 9, wherein the defining of the body of the resistor includes defining the body of the resistor to comprise a region of the lightly doped volume between the portion of the channel stopper and the contact region.
Claim 13
Dependent Claim
17 words
The method of claim 10, wherein the region of the lightly doped volume is an unbounded region.
Claim 14
Dependent Claim
21 words
The method of claim 11, wherein the defining of the second terminal includes defining the contact region on the substrate surface.
Claim 15
Dependent Claim
27 words
The method of claim 11, wherein the defining of the second terminal includes defining the contact region on the surface of a doped well in the substrate.
Claim 16
Dependent Claim
27 words
The method of claim 11, further comprising coupling the first terminal to a positive power supply potential V dd so that the resistor constitutes a pull-up resistor.
Claim 17
Dependent Claim
27 words
The method of claim 11, further comprising coupling the first terminal to a negative power supply potential V SS so that the resistor constitutes a pull-down resistor.
Claim 18
Dependent Claim
39 words
The method of claim 11, further comprising positioning the resistor and an associated active circuit component to minimize the surface area of the substrate occupied, so that more circuits are fabricated on a given surface area of the substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |