Programmable logic bias driver

Claim 1

A circuit for biasing a plurality of differential amplifiers distributed across a semiconductor device having a programmable logic array, wherein each of the differential amplifiers includes an NMOS transistor current source that has a gate terminal for receiving a bias voltage that controls a bias current in the differential amplifier and wherein each of the differential amplifiers includes a load resistor having a resistance that varies due to a semiconductor processing variation effect that occurs during fabrication such that a gain of each of the plurality of differential amplifiers is subject to a variation from an expected value, comprising: a bias voltage generator, coupled to each of the plurality of NMOS transistor current sources, for generating the bias voltage in response to a regulated current; a current generator for generating a reference current, said current generator including a resistor subject to the semiconductor processing variation effect to adjust said reference current to compensate for the variation in the gain; a temperature compensator, coupled to said current generator, for producing said regulated current from said reference current, said temperature compensator further including a first and a second bipolar transistor, each said bipolar transistor including a base, a collector and an emitter, with said collectors of said bipolar transistors coupled to a summing node, and said emitter of said first bipolar transistor coupled to a reference voltage; a resistor, having a first terminal coupled to said emitter of said second bipolar transistor and a second terminal coupled to said reference voltage, and a third bipolar transistor, having a base coupled to a collector thereof and an emitter coupled to said reference voltage, said collector of said third bipolar transistor coupled to said current generator for establishing a base voltage and base current; wherein said bases of said first and second bipolar transistors are each coupled to said base of said third bipolar transistor, and said first bipolar transistor and said second bipolar transistor are responsive to said base current and said base voltage to generate, respectively, a first current through said first bipolar transistor and a second current through said second bipolar transistor and said resistor such that said regulated current is produced at said summing node as a sum of said first current and said second current with said first current having an inverse relationship to a temperature variation of the semiconductor device and said second current having a direct relationship to said temperature variation; and a current mirror, coupled to said temperature compensator and to said bias voltage generator, for mirroring said regulated current produced in said temperature compensator to said bias voltage generator.