High throughput FPGA control interface

Claim 2

A programable logic device (PLD) comprising: at least one control data port for receiving a plurality of serial configuration data channels from an external source; a control bus for routing the plurality of configuration data channels from the control data port; a plurality of programable blocks; a plurality of storage devices within each programable block for receiving and storing configuration data; and an address circuit within each programable block coupled to one channel of the control bus and coupled by address lines to each of the storage devices.

Claim 3

The PLD of claim 1 wherein failure of one of the programable blocks does not affect any other of the programmable blocks, the control bus, and the at least one control data port.

Claim 4

The PLD of claim 1 wherein the address circuit and at least one data line for each programmable block are electrically independent from the address circuit and at least one data line of each other programmable block.

Claim 5

The PLD of claim 1 wherein the storage devices are arranged as an array of N rows and M columns and the address circuit further comprises: an N-bit row register coupled to the at least one data line and having row lines extending only from the row register across the M columns; an M-bit column register coupled to the at least one data line and having column lines extending from the column register only across the N-rows.

Claim 6

The PLD of claim 4 wherein the row register and column register are each coupled to at least two data lines and are loaded in parallel.

Claim 7

The PLD of claim 5 wherein the row register and column register are each coupled to only one data line and are loaded in serial.

Claim 8

A single chip programmable logic device (PLD) comprising: a plurality of programmable tiles organized in blocks wherein each block comprises a unique subset of the plurality of programmable tiles; a data bus extending to each of the blocks; independent address means for each block, the address means coupled to the data bus; an independent block enable line coupled to each block such that when the block enable line is asserted the address means of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address means, the assertion and deassertion of the block enable line coupled to each block being independent of the assertion and deassertion of any other block enable line wherein any combination of blocks in a row is enabled to receive said data.

Claim 9

A single chip programmable logic device (PLD) comprising: a plurality of programmable tiles organized in blocks wherein each block comprises a unique subset of the plurality of programmable tiles; a data bus extending to each of the blocks; independent address means for each block, the address means coupled to the data bus; an independent block enable line coupled to each block such that when the block enable line is asserted the address means of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address means, the assertion and deassertion of the block enable line coupled to each block being independent of the assertion and deassertion of any other block enable line wherein any combination of blocks in a row is enabled to receive said data.

Claim 10

A programmable device (PLD) comprising: an array of switches; a plurality of logical blocks, wherein each logical block comprises a unique subset of the array of switches, each switch uniquely identifiable by a row address, a column address, and a block address; a block select bus for supplying the block address to selected ones of the array of switches; a plurality of row select lines supplying the row address to selected ones of the array of switches; and a plurality of column lines supplying the column address to selected ones of the array of switches.

Claim 11

A programmable device (PLD) comprising: an array of switches; a plurality of logical blocks, wherein each logical block comprises a unique subset of the array of switches, each switch uniquely identifiable by a row address, a column address, and a block address; a block select bus for supplying the block address to selected ones of the array of switches; a plurality of row select lines supplying the row address to selected ones of the array of switches; and a plurality of column lines supplying the column address to selected ones of the array of switches.

Claim 12

The programmable device (PLD) of claim 8 further comprising: at least one data line coupled to each of the plurality of logical blocks for supplying a configuration data stream to the logical blocks; a register in each logical block having a data input coupled to the at least one data line, an enable input coupled to the block select bus, and having outputs coupled to the row select lines, and the column lines.

Claim 13

The programmable device of claim 8 wherein the row select lines and column select lines are physically constrained in length to a single one of the plurality of logical blocks.

Claim 14

A single chip programmable logic device (PLD) having a plurality of programmable logic blocks formed integrally on the single chip, each programmable logic block comprising: a plurality of storage devices for receiving and storing configuration data; a select line for receiving a signal to enable the programmable logic block, said signal being independent of the operation of any other programmable logic block in said plurality of programmable logic blocks so that any combination of said plurality of programmable logic blocks in a row can be enabled; at least one data line coupled to the plurality of storage devices for supplying configuration data; and an address circuit for enabling a selected number of the plurality of storage devices in the block to store configuration data from the at least one data line.

Claim 15

A single chip programmable logic device (PLD) having a plurality of programmable logic blocks formed integrally on the single chip, each programmable logic block comprising: a plurality of storage devices for receiving and storing configuration data; a select line for receiving a signal to enable the programmable logic block, said signal being independent of the operation of any other programmable logic block in said plurality of programmable logic blocks so that any combination of said plurality of programmable logic blocks in a row can be enabled; at least one data line coupled to the plurality of storage devices for supplying configuration data; and an address circuit for enabling a selected number of the plurality of storage devices in the block to store configuration data from the at least one data line.

Claim 16

A programmable logic device (PLD) having a plurality of programmable logic blocks, each programmable logic block comprising: a plurality of storage devices for receiving and storing configuration data; a select line for receiving a signal to enable the programmable logic block; at least one data line coupled to the plurality of storage devices for supplying configuration data; and an address circuit for enabling a selected number of the plurality of storage devices in the block to store configuration data from the at least one data line, wherein the address circuit comprises: a first clock line; a second clock line; a first shift register having a data input coupled to the data line and having a first clock input and having an enable input coupled to the select line; a plurality of address lines extending from each bit of the first shift register and terminating at the width of the programmable logic block; a second shift register having a data input coupled to the data line and having a second clock input and having an enable input coupled to the select line; a plurality of data lines extending from each bit of the second shift register and terminating at the length of the programmable logic block.

Claim 17

A programmable logic device (PLD) having a plurality of programmable logic blocks, each programmable logic block comprising: a plurality of storage devices for receiving and storing configuration data; a select line for receiving a signal to enable the programmable logic block; at least one data line coupled to the plurality of storage devices for supplying configuration data; and an address circuit for enabling a selected number of the plurality of storage devices in the block to store configuration data from the at least one data line, wherein the address circuit comprises: a first clock line; a second clock line; a first shift register having a data input coupled to the data line and having a first clock input and having an enable input coupled to the select line; a plurality of address lines extending from each bit of the first shift register and terminating at the width of the programmable logic block; a second shift register having a data input coupled to the data line and having a second clock input and having an enable input coupled to the select line; a plurality of data lines extending from each bit of the second shift register and terminating at the length of the programmable logic block.

Claim 18

A programmable logic device (PLD) comprising: a plurality of programmable tiles, each tile comprising plurality of programmable storage devices; a plurality of logic blocks, wherein each logic block comprises a unique set of the programmable tiles; a first clock line coupled to each logic block; a second clock line coupled to each logic block; a data line coupled to each logic block; an enable line coupled to each logic block; an address circuit within each logic block responsive to the first clock line, the second clock line, the data line, and the enable line, wherein the address circuit has a plurality of address lines extending only to each of the programmable tiles within the logic block, the address circuit capable of transferring data received from the data line to selected ones of the programmable logic elements within the block when a preselected signal is received on the enable line.

Claim 19

A programmable logic device (PLD) comprising: a plurality of programmable tiles, each tile comprising plurality of programmable storage devices; a plurality of logic blocks, wherein each logic block comprises a unique set of the programmable tiles; a first clock line coupled to each logic block; a second clock line coupled to each logic block; a data line coupled to each logic block; an enable line coupled to each logic block; an address circuit within each logic block responsive to the first clock line, the second clock line, the data line, and the enable line, wherein the address circuit has a plurality of address lines extending only to each of the programmable tiles within the logic block, the address circuit capable of transferring data received from the data line to selected ones of the programmable logic elements within the block when a preselected signal is received on the enable line.