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US5654576A
Expired / Lapsed
US
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Post-titanium nitride mask ROM programming method and device manufactured thereby
Assignee: United Microelectronics Corp
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Filing: 1995-11-16
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Granted: 1997-08-05
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Expires: 2015-11-16
Abstract
Abstract A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Yi-Chung Sheng
- 👤 Shing-Ren Sheu
- 👤 Chen-Hui Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:59
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
A mask ROM semiconductor device on a semiconductor substrate with an array of parallel buried bit lines integral therewith, said buried bit lines being oriented in a first direction, a gate oxide layer above said substrate and word lines formed above said gate oxide layer, the device comprising: a dielectric layer over said word lines, said dielectric layer having a thickness between 2,000 Å and 4,000 Å; a contact hole in said dielectric layer; a patterned titanium nitride layer over said device extending into said contact hole, said TiN layer having a ROM code opening therethrough, said titanium nitride layer having a step height; wherein said step height is less than 700 Å; a ROM code ion implanted region below said ROM code opening located between a pair of said bit lines; an ion implanted code implant dopant in a doped region in said substrate, the code implant having been annealed; and patterned metallization.
Claim 2
Dependent Claim
154 words
A mask ROM semiconductor device on a semiconductor substrate with an array of parallel buried bit lines integral therewith, said buried bit lines being oriented in a first direction, a gate oxide layer above said substrate and word lines formed above said gate oxide layer, the device comprising: a dielectric layer over said word lines, said dielectric layer having a thickness between 2,000 Å and 4,000 Å; a contact hole in said dielectric layer; a patterned titanium nitride layer over said device extending into said contact hole, said TiN layer having a ROM code opening therethrough, said titanium nitride layer having a step height; wherein said step height is less than 700 Å; a ROM code ion implanted region below said ROM code opening located between a pair of said bit lines; an ion implanted code implant dopant in a doped region in said substrate, the code implant having been annealed; and patterned metallization.
Claim 3
Dependent Claim
11 words
The device of claim 1 wherein said dielectric layer comprises BPSG.
Claim 4
Dependent Claim
20 words
The device of claim 1 wherein said step height is within the range of between 400 Å and 700 Å.
Claim 5
Dependent Claim
23 words
The device of claim 3 wherein said dielectric has a thickness of about 3,000 Å and said step height is about 500 Å.
Claim 6
Dependent Claim
17 words
The device of claim 1 wherein said dielectric layer comprises a material selected from BPSG and BPTEOS.
Claim 7
Dependent Claim
15 words
The device of claim 5 wherein said dielectric has a thickness of about 3,000 Å.
Claim 8
Dependent Claim
13 words
The device of claim 3 wherein said step height is about 500 Å.
Claim 9
Dependent Claim
13 words
The device of claim 2 wherein said step height is about 500 Å.
Claim 10
Dependent Claim
17 words
The device of claim 7 wherein said dielectric layer comprises a material selected from BPSG and BPTEOS.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |