US5652861A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for interleaving memory modules and banks
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-07-26
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Granted: 1997-07-29
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Expires: 2016-07-26
Abstract
Abstract A memory system for a digital computer has first and second memory modules having differing numbers of independently-accessible banks and unlike capacities. The digital computer also has an addressing arrangement that employs horizontal stacking for interleaving together the banks of both the first and second memory modules, such that the first memory module is interleaved to a first level and the second memory module to a second, different level. The invention also embraces a method of interleaving the memory system employing horizontal stacking. In usual applications, horizontal stacking permits the memory system to be interleaved to a higher level than that achieved by conventional vertical stacking schemes.
Inventors
- 👤 David T. Mayo
- 👤 David W. Hartwell
- 👤 Hansel A. Collins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F12/0646; G06F12/0653
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
112 words
A memory apparatus comprising: A) a first memory module having a first number of independently-accessible banks; B) a second memory module having a second number of independently-accessible banks, said second number being different from said first number; and C) addressing means coupled with said first and second memory modules for interleaving said first and second memory modules to a first level of interleaving, and for internally interleaving said banks of said first memory module to a second level of interleaving that differs from said first level of interleaving and said banks of said second memory module to a third level of interleaving that differs from said first and second levels of interleaving.
Claim 2
Dependent Claim
112 words
A memory apparatus comprising: A) a first memory module having a first number of independently-accessible banks; B) a second memory module having a second number of independently-accessible banks, said second number being different from said first number; and C) addressing means coupled with said first and second memory modules for interleaving said first and second memory modules to a first level of interleaving, and for internally interleaving said banks of said first memory module to a second level of interleaving that differs from said first level of interleaving and said banks of said second memory module to a third level of interleaving that differs from said first and second levels of interleaving.
Claim 3
Dependent Claim
48 words
The memory system in accordance with claim 1, further comprising translation means coupled with said first and second memory modules and said addressing means for translating a plurality of logical addresses into a plurality of physical addresses of said memory banks of said first and second memory modules.
Claim 4
Dependent Claim
14 words
The memory system in accordance with claim 1, wherein said first number is two.
Claim 5
Dependent Claim
91 words
A memory apparatus comprising: A) a first memory module having a plurality of independently-accessible banks; B) a second memory module having a plurality of independently-accessible banks; and C) addressing means coupled with said first and second memory modules for interleaving said memory modules to a first level of interleaving, and internally interleaving said banks of said first memory module and internally interleaving said banks of second memory module, to interleave the first and second memory modules to one or more levels of interleaving that differ from said first level of interleaving.
Claim 6
Dependent Claim
91 words
A memory apparatus comprising: A) a first memory module having a plurality of independently-accessible banks; B) a second memory module having a plurality of independently-accessible banks; and C) addressing means coupled with said first and second memory modules for interleaving said memory modules to a first level of interleaving, and internally interleaving said banks of said first memory module and internally interleaving said banks of second memory module, to interleave the first and second memory modules to one or more levels of interleaving that differ from said first level of interleaving.
Claim 7
Dependent Claim
48 words
The memory system in accordance with claim 4, further comprising translation means coupled with said first and second memory modules and said addressing means for translating a plurality of logical addresses into a plurality of physical addresses of said memory banks of said first and second memory modules.
Claim 8
Dependent Claim
97 words
A memory apparatus comprising: A. a plurality of memory modules each having one or more independently-accessible banks, with at least one of said modules having more than one bank and certain banks having larger capacities than others; B. addressing means coupled to said plurality of memory modules for associating together modules with smaller capacity banks and interleaving the associated modules and the larger-capacity bank modules to a first level of interleaving, and for further internally interleaving the banks within each memory module to one or more levels of interleaving that differ from the first level of interleaving.
Claim 9
Dependent Claim
97 words
A memory apparatus comprising: A. a plurality of memory modules each having one or more independently-accessible banks, with at least one of said modules having more than one bank and certain banks having larger capacities than others; B. addressing means coupled to said plurality of memory modules for associating together modules with smaller capacity banks and interleaving the associated modules and the larger-capacity bank modules to a first level of interleaving, and for further internally interleaving the banks within each memory module to one or more levels of interleaving that differ from the first level of interleaving.
Claim 10
Dependent Claim
48 words
The memory system in accordance with claim 6, further comprising translation means coupled with said first and second memory modules and said addressing means for translating a plurality of logical addresses into a plurality of physical addresses of said memory banks of said first and second memory modules.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |