EP0380855A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
Assignee: Digital Equipment Corp
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Filing: 1989-09-13
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Granted: —
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Expires: 2009-09-13
Abstract
Abstract A multi-processing computer system including a plurality of central processing units (CPUs) (12) and input/output (I/O) units (18, 20), a system memory (16) including a plurality of DRAM-based memory segments, a system control unit (SCU) (14) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data. The system memory (16) is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read data from addressed memory segments to the interface for transfer to the SCU, a second dedicated data path for transfer of write data received from the SCU through the interface to addressed memory segments, and a third dedicated path for transfer of addresses from the SCU to identify addressed segments of memory.
Inventors
- 👤 John Lynch
- 👤 Kumar Chinnaswamy
- 👤 Michael A. Gagliardo
- 👤 James E. Tessari
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 09:11
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
174 words
A multi-processing computer system characterised by: a system memory (16) for storage of data comprising at least one memory unit containing independently accessible memory segments; a system control unit (SCU) (14) for operating a plurality of processors in parallel, the SCU being operative to accept memory commands, decode memory addresses accompanying the memory commands, and accommodate transfer of data to and from a system unit originating a memory command and corresponding addressed memory segments; interface means (30) for establishing communication between the SCU (14) and the system memory (16), each of the memory units comprising the system memory (16) including means for providing a dedicated read data path for the transfer of read data from addressed memory segments to the interface means (30) for transfer to the SCU (14); means for providing a dedicated write data path for the transfer of write data received from the SCU (14) through the interface means (30) to addressed memory segments; and means for providing a dedicated address path for transfer of memory addresses from the SCU (14).
Claim 2
Dependent Claim
174 words
A multi-processing computer system characterised by: a system memory (16) for storage of data comprising at least one memory unit containing independently accessible memory segments; a system control unit (SCU) (14) for operating a plurality of processors in parallel, the SCU being operative to accept memory commands, decode memory addresses accompanying the memory commands, and accommodate transfer of data to and from a system unit originating a memory command and corresponding addressed memory segments; interface means (30) for establishing communication between the SCU (14) and the system memory (16), each of the memory units comprising the system memory (16) including means for providing a dedicated read data path for the transfer of read data from addressed memory segments to the interface means (30) for transfer to the SCU (14); means for providing a dedicated write data path for the transfer of write data received from the SCU (14) through the interface means (30) to addressed memory segments; and means for providing a dedicated address path for transfer of memory addresses from the SCU (14).
Claim 3
Dependent Claim
42 words
A multi-processing system as claimed in Claim 1 wherein each of the memory segments comprising the system memory (16) comprises a plurality of banks of DRAMs, the banks having memory addresses which are interleaved on boundaries of blocks having a predetermined size.
Claim 4
Dependent Claim
71 words
A multi-processing system as claimed in Claim 1 or Claim 2 wherein the means for providing the read data path includes: means for accessing addressed segments and banks of memory to retrieve data stored therein; means for translating the retrieved data to preferred logic levels; and means for transferring selected groups of stored data to the interface means (30) according to a selected order for subsequent transfer to the SCU (14).
Claim 5
Dependent Claim
71 words
A multi-processing system as claimed in any one of the preceding claims wherein the means for providing the write data path includes: means for accepting and storing data to be written to memory from the interface means (30) in selectively ordered data groups; means for translating the data to preferred logic levels; and means for accessing addressed segments and banks of memory in order to store therein the received write data.
Claim 6
Dependent Claim
76 words
A multi-processing system as claimed in Claim 4 when dependent upon Claim 3 wherein the system memory (16) further includes means for reading data that is being written to addressed segments of memory without accessing the addressed memory segments by transferring write data from the means for storing write data directly to the means for storing read data so that the transferred write data may subsequently be transferred as read data to the interface means (30).
Claim 7
Dependent Claim
41 words
A multi-processing system as claimed in any one of the preceding claims wherein the system memory (16) further comprises means for generating control signals for controlling the operation of the means providing the read data path and the write data path.
Claim 8
Dependent Claim
50 words
A multi-processing system as claimed in Claim 6 wherein the system memory (16) further includes: means for accepting control signals for system memory DRAMs; means for generating corresponding memory control commands in response thereto; and means for transferring selected ones of the DRAM control signals to corresponding addressed memory segments.
References Cited (Backward Citations)
No citation records indexed.
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