Method of forming a stacked capacitor with a double wall crown shape

Claim 1

A method of fabricating a stacked capacitor having a double wall crown shape, comprising the steps of: a) forming a first insulating layer over a substrate; b) forming a barrier layer over said first insulation layer; c) etching a node contact opening through said barrier layer and said first insulation layer exposing said substrate; d) forming a first conductive layer filling said node contact opening and covering said barrier layer; e) forming a masking block over at least said node contact opening, said masking block having sidewalls; f) forming first conductive spacers on said sidewalls of said masking block, said first conductive spacers having sidewalls; g) forming dielectric spacers on said sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; h) forming second conductive spacers on the sidewalls of said dielectric spacers, said second conductive spacers having sidewalls; i) anisotropically etching said first conductive layer using said masking block, first conductive spacers, said dielectric spacers and said second conductive spacers as a mask; j) selectively removing said masking block and said dielectric spacers, thereby forming a bottom electrode; k) forming a capacitor dielectric layer over said bottom electrode; and l) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor.

Claim 2

A method of fabricating a stacked capacitor having a double wall crown shape, comprising the steps of: a) forming a first insulating layer over a substrate; b) forming a barrier layer over said first insulation layer; c) etching a node contact opening through said barrier layer and said first insulation layer exposing said substrate; d) forming a first conductive layer filling said node contact opening and covering said barrier layer; e) forming a masking block over at least said node contact opening, said masking block having sidewalls; f) forming first conductive spacers on said sidewalls of said masking block, said first conductive spacers having sidewalls; g) forming dielectric spacers on said sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; h) forming second conductive spacers on the sidewalls of said dielectric spacers, said second conductive spacers having sidewalls; i) anisotropically etching said first conductive layer using said masking block, first conductive spacers, said dielectric spacers and said second conductive spacers as a mask; j) selectively removing said masking block and said dielectric spacers, thereby forming a bottom electrode; k) forming a capacitor dielectric layer over said bottom electrode; and l) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor.

Claim 15

A method of fabrication of dynamic random access memory (DRAM) cell having a stacked capacitor with a double wall crown shape, comprising the steps of a) providing a MOS (metal oxide semiconductor) device having a gate electrode, source and drain regions adjacent to a field oxide region in a substrate, a conductive word line formed over said field oxide region; b) forming first insulating layer over the resultant surface; c) forming a barrier layer over said first insulation layer; d) etching a node contact opening through said barrier layer and said first insulation layer exposing said source region in said substrate; e) forming a first conductive layer in said node contact opening and covering said barrier layer; f) forming a masking layer over said first conductive layer; g) etching said masking layer forming a masking block over at least said node contact hole; h) forming a second conductive layer over the surfaces of said masking block and said first conductive layer; i) anisotropically etching said second conductive layer forming first conductive spacers on the sidewalls of said masking block, said first conductive spacers having sidewalls; j) forming a dielectric layer over at least said masking block and said first conductive spacers; k) anisotropically etching said dielectric layer forming dielectric spacers on the sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; l) forming a third conductive layer over at least said masking block, said first conductive spacers, and said dielectric spacers; m) anisotropically etching said third conductive layer forming second conductive spacers on the sidewalls of said dielectric spacers; n) anisotropically etching said first conductive layer using said masking block, first conductive spacers, said dielectric spacers and said second conductive spacers as a mask, thereby exposing said barrier layer; o) removing said masking block, and said dielectric spacers, thereby forming a bottom electrode; p) forming a capacitor dielectric layer over said bottom electrode; q) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor; and r) forming an insulating layer and metal lines over said stacked capacitor to complete said DRAM cell.

Claim 16

A method of fabrication of dynamic random access memory (DRAM) cell having a stacked capacitor with a double wall crown shape, comprising the steps of a) providing a MOS (metal oxide semiconductor) device having a gate electrode, source and drain regions adjacent to a field oxide region in a substrate, a conductive word line formed over said field oxide region; b) forming first insulating layer over the resultant surface; c) forming a barrier layer over said first insulation layer; d) etching a node contact opening through said barrier layer and said first insulation layer exposing said source region in said substrate; e) forming a first conductive layer in said node contact opening and covering said barrier layer; f) forming a masking layer over said first conductive layer; g) etching said masking layer forming a masking block over at least said node contact hole; h) forming a second conductive layer over the surfaces of said masking block and said first conductive layer; i) anisotropically etching said second conductive layer forming first conductive spacers on the sidewalls of said masking block, said first conductive spacers having sidewalls; j) forming a dielectric layer over at least said masking block and said first conductive spacers; k) anisotropically etching said dielectric layer forming dielectric spacers on the sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; l) forming a third conductive layer over at least said masking block, said first conductive spacers, and said dielectric spacers; m) anisotropically etching said third conductive layer forming second conductive spacers on the sidewalls of said dielectric spacers; n) anisotropically etching said first conductive layer using said masking block, first conductive spacers, said dielectric spacers and said second conductive spacers as a mask, thereby exposing said barrier layer; o) removing said masking block, and said dielectric spacers, thereby forming a bottom electrode; p) forming a capacitor dielectric layer over said bottom electrode; q) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor; and r) forming an insulating layer and metal lines over said stacked capacitor to complete said DRAM cell.

Claim 24

A method of fabricating a stacked capacitor having a double walled cylindrical, shape, comprising the steps of: a) forming first insulating layer over a substrate; b) forming a barrier layer composed of silicon oxide over said first insulation layer; c) etching a node contact opening through said barrier layer and said first insulation layer exposing said substrate; d) forming a first conductive layer of polysilicon filling said node contact opening and covering said barrier layer; said first conductive layer is formed of polysilicon doped with an impurity selected from the group consisting of phosphorus and arsenic, and said first conductive layer has an impurity concentration in a range of between about 1E19 and 1E21 atoms/cm 3 and a thickness over said first insulating layer in a range of between about 1000 and 3000 Å; e) forming a masking layer composed of silicon nitride over said first conductive layer; f) patterning said masking layer forming a masking block over at least said node contact hole; said masking block has a cylindrical shape and a height in a range of between about 4000 and 8000 Å; g) forming a second conductive layer of in situ doped polysilicon over the surfaces of said masking block and said first conductive layer; h) anisotropically etching said second conductive layer forming first conductive spacers on the sidewalls of said masking block; said first conductive spacers are formed of a material selected from the group consisting of polysilicon and polycide, and have a height of between about 4000 and 8000 Å, and have a thickness in the range of between about 800 and 2500 Å; i) forming a dielectric layer composed of silicon nitride over at least said masking block and said first conductive spacers; j) anisotropically etching said dielectric layer forming dielectric spacers on the sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; said dielectric spacers having a thickness in a range of between about 800 and 2500 Å; k) forming a third conductive layer composed of polysilicon over at least said masking block, said first conductive spacers and said dielectric spacers; l) anisotropically etching said third conductive layer forming second conductive spacers on the sidewalls of said dielectric spacers, said second conductive spacers having sidewalls; said second conductive spacers are formed of a material selected from the group consisting of polysilicon and polycide, and have a height of between about 4000 and 8000 Å, and have a thickness in a range of between about 800 and 2500 Å; m) anisotropically etching said first conductive layer using said cylinder block, first conductive spacers, said dielectric spacers and said second conductive spaces as a mask thereby exposing said barrier layer; n) selectively removing said masking block, and said dielectric spacers, thereby forming a bottom electrode; o) forming a capacitor dielectric layer over said bottom electrode; and p) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor.

Claim 25

A method of fabricating a stacked capacitor having a double walled cylindrical, shape, comprising the steps of: a) forming first insulating layer over a substrate; b) forming a barrier layer composed of silicon oxide over said first insulation layer; c) etching a node contact opening through said barrier layer and said first insulation layer exposing said substrate; d) forming a first conductive layer of polysilicon filling said node contact opening and covering said barrier layer; said first conductive layer is formed of polysilicon doped with an impurity selected from the group consisting of phosphorus and arsenic, and said first conductive layer has an impurity concentration in a range of between about 1E19 and 1E21 atoms/cm 3 and a thickness over said first insulating layer in a range of between about 1000 and 3000 Å; e) forming a masking layer composed of silicon nitride over said first conductive layer; f) patterning said masking layer forming a masking block over at least said node contact hole; said masking block has a cylindrical shape and a height in a range of between about 4000 and 8000 Å; g) forming a second conductive layer of in situ doped polysilicon over the surfaces of said masking block and said first conductive layer; h) anisotropically etching said second conductive layer forming first conductive spacers on the sidewalls of said masking block; said first conductive spacers are formed of a material selected from the group consisting of polysilicon and polycide, and have a height of between about 4000 and 8000 Å, and have a thickness in the range of between about 800 and 2500 Å; i) forming a dielectric layer composed of silicon nitride over at least said masking block and said first conductive spacers; j) anisotropically etching said dielectric layer forming dielectric spacers on the sidewalls of said first conductive spacers, said dielectric spacers having sidewalls; said dielectric spacers having a thickness in a range of between about 800 and 2500 Å; k) forming a third conductive layer composed of polysilicon over at least said masking block, said first conductive spacers and said dielectric spacers; l) anisotropically etching said third conductive layer forming second conductive spacers on the sidewalls of said dielectric spacers, said second conductive spacers having sidewalls; said second conductive spacers are formed of a material selected from the group consisting of polysilicon and polycide, and have a height of between about 4000 and 8000 Å, and have a thickness in a range of between about 800 and 2500 Å; m) anisotropically etching said first conductive layer using said cylinder block, first conductive spacers, said dielectric spacers and said second conductive spaces as a mask thereby exposing said barrier layer; n) selectively removing said masking block, and said dielectric spacers, thereby forming a bottom electrode; o) forming a capacitor dielectric layer over said bottom electrode; and p) forming a top plate electrode over said capacitor dielectric layer to form said stacked capacitor.