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US5652157A
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Forming a gate electrode on a semiconductor substrate by using a T-shaped dummy gate
Assignee: NTT Inc
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Filing: 1996-02-28
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Granted: 1997-07-29
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Expires: 2016-02-28
Abstract
Abstract A new design concept is presented and demonstrated for the fabrication of active and passive components in integrated circuit (IC) devices for microwave signal transmission. High circuit packing density is desirable but the current configurations of the conventional flat strip type conductors present physical limitations to achieving such an objective. The new conductor configuration not only overcomes such circuit packing problems of the conventional line design, but provides additional improvements in performance parameters, such as lower resistance and lower parasitic interactions, an ability to fabricate circuits to design specifications and to improve reliability at low cost. The new concept has been applied to the fabrication of transmission lines, capacitors, inductors, air bridges and to formulating the fabrication steps for a FET. Polyamide film enables an improved fabrication step to be performed in the invention, and a new processing technique for polyimide material has also been demonstrated.
Inventors
- 👤 Makoto Hirano
- 👤 Kazuyoshi Asai
- 👤 Yuhki Imai
- 👤 Masami Tokumitsu
- 👤 Tsuneo Tokumitsu
- 👤 Ichihiko Toyoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/0126; H10D86/00; H10D86/80; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/432; H10W20/435; H10W20/497; H10W44/00; H10W44/20; H10W44/203; H10W44/216
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
252 words
A process of fabricating a gate electrode on semiconducting substrate material, said gate electrode means formed in a shape of a deep and narrow conductor having a depth larger than width to minimize signal interference effects in an integrated circuit of a three dimensional architecture, said process comprising the steps of: (a) forming a dummy gate of a T-shaped configuration on said semiconducting substrate material; (b) processing said substrate material to fabricate active regions on said substrate material in exposed regions; (c) forming a first insulation layer on the surface of said substrate material and on the surface of the dummy gate; (d) removing the dummy gate; (e) forming a first insulation film on the surface of said substrate material; (f) forming a photoresist masking layer on said insulation film to define a window region having an window cavity of a narrow and deep shape (a N&D configuration) for forming a gate electrode; (g) fabricating said window cavity of the N&D configuration by removing the photoresist layer from the window region; (h) forming a first conductive layer on said window cavity and on surrounding regions; (i) depositing a second conductive layer in the form of a conductive deposit, wherein said first conductive layer is adapted for use as a depositing electrode, so as to fill said window cavity completely; (j) forming a gate electrode masking layer on the conductive deposit to define the gate electrode; (k) removing the gate electrode masking layer thereby to form the gate electrode of the N&D configuration.
Claim 2
Dependent Claim
252 words
A process of fabricating a gate electrode on semiconducting substrate material, said gate electrode means formed in a shape of a deep and narrow conductor having a depth larger than width to minimize signal interference effects in an integrated circuit of a three dimensional architecture, said process comprising the steps of: (a) forming a dummy gate of a T-shaped configuration on said semiconducting substrate material; (b) processing said substrate material to fabricate active regions on said substrate material in exposed regions; (c) forming a first insulation layer on the surface of said substrate material and on the surface of the dummy gate; (d) removing the dummy gate; (e) forming a first insulation film on the surface of said substrate material; (f) forming a photoresist masking layer on said insulation film to define a window region having an window cavity of a narrow and deep shape (a N&D configuration) for forming a gate electrode; (g) fabricating said window cavity of the N&D configuration by removing the photoresist layer from the window region; (h) forming a first conductive layer on said window cavity and on surrounding regions; (i) depositing a second conductive layer in the form of a conductive deposit, wherein said first conductive layer is adapted for use as a depositing electrode, so as to fill said window cavity completely; (j) forming a gate electrode masking layer on the conductive deposit to define the gate electrode; (k) removing the gate electrode masking layer thereby to form the gate electrode of the N&D configuration.
Claim 3
Dependent Claim
23 words
The process of fabricating gate electrode as claimed in claim 1, wherein said depositing step includes electroplating and said conductive deposit is gold.
Claim 4
Dependent Claim
18 words
The process of fabricating gate electrode as claimed in claim 1, wherein said semiconducting substrate material is GaAs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |