US5116772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a junction field effect transisor
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1991-04-11
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Granted: 1992-05-26
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Expires: 2011-04-11
Abstract
Abstract The present invention provides a method for manufacturing a field effect transistor which overcomes problems occurring in the manufacture of InP material junction field effect transistors. Because the electron saturation velocity is higher than that of silicon or GaAs it is desirable to have a gate length shorter than the mask length as well as to have the source, drain, and gate metals evaporated by the self-aligned method. The present invention provides a method of achieving gate lengths of 1 μm or shorter without requiring an expensive electron beam apparatus or X-ray lighography apparatus.
Inventors
- 👤 Ki S. Park
- 👤 Sang B. Kim
- 👤 Kwang Y. Oh
- 👤 Yong T. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
A method for manufacturing a homojunction type field effect transistor comprising: a first epitaxy growth process for growing a N type InP channel layer on a semi-insulating substrate and, thereafter, growing a GaInAs(P) layer thereon, a first selective etching process of the GaInAs(P) layer for selectively anisotropically etching only the GaInAs(P) layer by using a selective etching solution, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type InP layer, to thereby form a gate electrode, a second selective etching process of the P type InP layer and the GaInAs(P) layer for etching selectively said InP layer using a gate metal as an etching mask and for forming under-cuts near both sides of the PN junction by selectively etching the GaInAs(P) layer which is exposed on surface after said second selective etching is completed, a source and a drain metal evaporation process for forming the source and the drain electrodes by evaporating the metal which is in ohmic contact with the N type InP layer, to thereby obtain a gate length L shorter than a length W on mask determined by the lithography method and to obtain the source and the drain electrodes by a self-aligning method.
Claim 2
Independent Claim
235 words
A method for manufacturing a homojunction type field effect transistor comprising: a first epitaxy growth process for growing a N type InP channel layer on a semi-insulating substrate and, thereafter, growing a GaInAs(P) layer thereon, a first selective etching process of the GaInAs(P) layer for selectively anisotropically etching only the GaInAs(P) layer by using a selective etching solution, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type InP layer, to thereby form a gate electrode, a second selective etching process of the P type InP layer and the GaInAs(P) layer for etching selectively said InP layer using a gate metal as an etching mask and for forming under-cuts near both sides of the PN junction by selectively etching the GaInAs(P) layer which is exposed on surface after said second selective etching is completed, a source and a drain metal evaporation process for forming the source and the drain electrodes by evaporating the metal which is in ohmic contact with the N type InP layer, to thereby obtain a gate length L shorter than a length W on mask determined by the lithography method and to obtain the source and the drain electrodes by a self-aligning method.
Claim 3
Dependent Claim
34 words
The method for manufacturing a homojunction type field effect transistor of claim 1, wherein the P type InP layer formed in said second epitaxy process is grown by a liquid phase epitaxy (LPE) method.
Claim 4
Dependent Claim
35 words
The method for manufacturing a homojunction type field effect transistor of claim 1, wherein the P type InP layer formed in said second epitaxy process is grown by the organometallic vapor phase epitaxy (OMVPE) method.
Claim 5
Dependent Claim
51 words
The method for manufacturing a homojunction type field effect transistor of claim 1, wherein, in said source and drain metal evaporation process, the metal is evaporated on entire surface without distinction of the electrodes by the lift-off method using the under-cut formed in previous process, to thereby form a self-aligned structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |