Patent US4834172A successfully refreshed from Google Patents.
Patent US5651130A successfully refreshed from Google Patents.
US5651130A
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Memory controller that dynamically predicts page misses
Assignee: Hewlett Packard Development Co LP
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Filing: 1995-10-17
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Granted: 1997-07-22
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Expires: 2015-10-17
Abstract
Abstract A memory controller dynamically predicts whether a next memory cycle which is not yet available will result in a page miss or page hit condition. RAS lines are selectively precharged if the next memory cycle is predicted to be a page miss. The memory controller keeps track of various combinations of types of cycles when a type of memory cycle is followed by a type of non-memory pending cycle. For each such combination, the memory controller determines the percentage of combinations which result in a page hit on the next memory cycle. Using this history, the memory controller selectively precharges the RAS lines when a certain combination of types of cycles indicates a percentage of hits is below a predicted threshold. If a number of page hits exceeds the predicted threshold, precharging is not performed.
Inventors
- 👤 Lee B. Hinkle
- 👤 Gary W. Thome
- 👤 Paul A. Santeler
- 👤 David R. Wooten
- 👤 John A. Landry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:06
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G06; G06F; G06F12/00; G06F12/02; G06F12/0215; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
265 words
A memory controller for controlling page mode dynamic random access memory devices in a computer system, the computer system executing cycles, the cycles having cycle types, a portion of which cycles and cycle types are directed to and performed by the dynamic random access memory devices and a remaining portion of which cycles and cycle types are directed to and performed by other devices in the computer system or are idle cycle types, the dynamic random access memory devices including row and column address strobe inputs and requiring precharging, the memory controller comprising: means for determining presence of a cycle and cycle type directed to and performed by the dynamic random access memory devices as a first cycle; means for determining when a cycle is performed by the other devices in the computer system or is an idle cycle type as a second cycle; and means coupled to said means for determining presence of said first cycle and said means for determining the performance of said second cycle for providing row and column address strobe signals to said dynamic random access memory devices to control operation of the dynamic random access memory devices, said means for providing row and column address strobe signals selectively keeping said row address strobe signal asserted based on the cycle type of said first cycle when said second cycle immediately follows said first cycle and deasserting said row address strobe signal and precharging said dynamic random access memory devices in remaining cases based on the cycle type of said first cycle when said second cycle immediately follows said first cycle.
Claim 2
Dependent Claim
265 words
A memory controller for controlling page mode dynamic random access memory devices in a computer system, the computer system executing cycles, the cycles having cycle types, a portion of which cycles and cycle types are directed to and performed by the dynamic random access memory devices and a remaining portion of which cycles and cycle types are directed to and performed by other devices in the computer system or are idle cycle types, the dynamic random access memory devices including row and column address strobe inputs and requiring precharging, the memory controller comprising: means for determining presence of a cycle and cycle type directed to and performed by the dynamic random access memory devices as a first cycle; means for determining when a cycle is performed by the other devices in the computer system or is an idle cycle type as a second cycle; and means coupled to said means for determining presence of said first cycle and said means for determining the performance of said second cycle for providing row and column address strobe signals to said dynamic random access memory devices to control operation of the dynamic random access memory devices, said means for providing row and column address strobe signals selectively keeping said row address strobe signal asserted based on the cycle type of said first cycle when said second cycle immediately follows said first cycle and deasserting said row address strobe signal and precharging said dynamic random access memory devices in remaining cases based on the cycle type of said first cycle when said second cycle immediately follows said first cycle.
Claim 3
Dependent Claim
77 words
The memory controller of claim 1, wherein the cycle types include idles, memory code reads, memory data reads, memory single writes and memory burst writes and wherein said means for providing row and column address strobe signals keeps said row address strobe signal asserted for memory code read and memory single write cycle types and deasserts said row address strobe signal and precharges said dynamic random access memory devices for memory data reads and memory burst writes.
Claim 4
Dependent Claim
94 words
The memory controller of claim 1, wherein the second cycle is performed by one of a plurality of other devices or is an idle cycle type and wherein said means for providing row and column address strobe signals further includes means for determining which of the plurality of other devices is performing said second cycle or whether said second cycle is an idle cycle type in selectively keeping based on a selection basis said row address strobe signal asserted or deasserting said row address strobe signal and precharging said dynamic random access memory devices.
Claim 5
Dependent Claim
48 words
The memory controller of claim 3, wherein said means for providing row and column address strobe signals includes means for dynamically changing the selection basis for keeping said row address strobe signal asserted or deasserting said row address strobe signal and precharging said dynamic random access memory devices.
Claim 6
Dependent Claim
79 words
The memory controller of claim 4, wherein said means for dynamically changing the selection basis includes means for determining whether to keep said row address strobe signal asserted or deassert said row address strobe signal and precharge said dynamic random access memory devices for a plurality of the combinations of cycle types of said first cycle and which of the plurality of other devices is performing said second cycle or whether said second cycle is an idle cycle type.
Claim 7
Dependent Claim
191 words
The memory controller of claim 5, wherein each of said means for determining whether to keep said row address strobe signal asserted or deassert said row address strobe signal and precharge said dynamic random access memory devices includes: means for counting a total number of occurrences of the cycle type of said first cycle followed by said second cycle performing device or idle condition, said means providing a total count; means for counting a number of occurrences of the cycle type of said first cycle followed by said second cycle performing device or idle condition wherein said second cycle was a page hit of said dynamic random access memory devices, said means providing a page hit count; means for determining when the total count of said means for counting total occurrences has reached a predetermined value; means for comparing the page hit count to a predetermined value when the total count of said means for counting total occurrences has reached said predetermined value; and means for indicating to keep the row address strobe signal asserted when the page hit count exceeds said predetermined value as determined by said means for comparing.
Claim 8
Dependent Claim
29 words
The memory controller of claim 6, wherein said predetermined value of said means for counting total occurrences and said predetermined value for comparing the page hit count are alterable.
Claim 9
Dependent Claim
47 words
The memory controller of claim 6, wherein said cycle types of said first cycle include data read burst cycles, code read burst cycles, single write cycles and burst write cycles and wherein the plurality of other devices performing cycles includes a cache controller and an external bus.
Claim 10
Dependent Claim
78 words
The memory controller of claim 8, wherein said means for determining whether to keep said row address strobe signal asserted or deassert said row address strobe signal and precharge said dynamic random access memory devices are provided for all but said data read burst cycles followed by cache cycles and code read burst cycles followed by cache cycles and for those cases said row address strobe signal is deasserted and said dynamic random access memory devices are precharged.
Claim 11
Independent Claim
222 words
A method for controlling page mode dynamic random access memory devices in a computer system, the computer system executing cycles, the cycles having cycle types, a portion of which cycles and cycle types are directed to and performed by the dynamic random access memory devices and a remaining portion of which cycles performed by other devices in the computer system or being idle cycle types, the dynamic random access memory devices including row and column address strobe inputs and requiring precharging, the method comprising the steps of: determining presence of a cycle and cycle type directed to and performed by the dynamic random access memory devices as a first cycle; determining when a cycle is performed by the other devices in the computer system or is an idle cycle type as a second cycle; and providing row and column address strobe signals to said dynamic random access memory devices to control operation of the dynamic random access memory devices by selectively keeping said row address strobe signal asserted based on the cycle type of said first cycle when said second cycle immediately follows said first cycle and deasserting said row address strobe signal and precharging said dynamic random access memory devices in remaining cases based on the cycle type of said first cycle when said second cycle immediately follows said first cycle.
Claim 12
Independent Claim
222 words
A method for controlling page mode dynamic random access memory devices in a computer system, the computer system executing cycles, the cycles having cycle types, a portion of which cycles and cycle types are directed to and performed by the dynamic random access memory devices and a remaining portion of which cycles performed by other devices in the computer system or being idle cycle types, the dynamic random access memory devices including row and column address strobe inputs and requiring precharging, the method comprising the steps of: determining presence of a cycle and cycle type directed to and performed by the dynamic random access memory devices as a first cycle; determining when a cycle is performed by the other devices in the computer system or is an idle cycle type as a second cycle; and providing row and column address strobe signals to said dynamic random access memory devices to control operation of the dynamic random access memory devices by selectively keeping said row address strobe signal asserted based on the cycle type of said first cycle when said second cycle immediately follows said first cycle and deasserting said row address strobe signal and precharging said dynamic random access memory devices in remaining cases based on the cycle type of said first cycle when said second cycle immediately follows said first cycle.
Claim 13
Dependent Claim
76 words
The method of claim 10, wherein the cycle types include idles, memory code reads, memory data reads, memory single writes and memory burst writes and wherein said step of providing row and column address strobe signals keeps said row address strobe signal asserted for memory code read and memory single write cycle types and deasserts said row address strobe signal and precharges said dynamic random access memory devices for memory data reads and memory burst writes.
Claim 14
Dependent Claim
90 words
The method of claim 10, wherein the second cycle is performed by one of a plurality of other devices or is an idle cycle type and wherein said step of providing row and column address strobe signals further determines which of the plurality of other devices is performing said second cycle or whether said second cycle is an idle cycle type in selectively keeping based on a selection basis said row address strobe signal asserted or deasserting said row address strobe signal and precharging said dynamic random access memory devices.
Claim 15
Dependent Claim
48 words
The method of claim 12, wherein said step of providing row and column address strobe signals includes the step of dynamically changing the selection basis for keeping said row address strobe signal asserted or deasserting said row address strobe signal and precharging said dynamic random access memory devices.
Claim 16
Dependent Claim
78 words
The method of claim 13, wherein said step of dynamically changing the selection basis includes the step of determining whether to keep said row address strobe signal asserted or deassert said row address strobe signal and precharge said dynamic random access memory devices for a plurality of combinations of cycle types of said first cycle and which of the plurality of other devices is performing said second cycle or whether said second cycle is an idle cycle type.
Claim 17
Dependent Claim
183 words
The method of claim 14, wherein said step of determining whether to keep said row address strobe signal asserted or deassert said row address strobe signal and precharge said dynamic random access memory devices for each case includes the steps of: counting a total number of occurrences of the cycle type of said first cycle followed by said second cycle performing device or idle condition, said counting providing a total count; counting a number of occurrences of the cycle type of said first cycle followed by said second cycle performing device or idle condition wherein said second cycle was a page hit of said dynamic random access memory devices, said counting providing a page hit count; determining when the total count of said means for counting total occurrences has reached a predetermined value; comparing the page hit count to a predetermined value when the total count of said means for counting total occurrences has reached said predetermined value; and indicating to keep the row address strobe signal asserted when the page hit count exceeds said predetermined value as determined by said comparing step.
Claim 18
Dependent Claim
31 words
The method of claim 15, wherein said predetermined value of said step of counting total occurrences and said predetermined value for said step of comparing the page hit count are alterable.
Claim 19
Dependent Claim
46 words
The method of claim 15, wherein said cycle types of said first cycle include data read burst cycles, code read burst cycles, single write cycles and burst write cycles and wherein the plurality of other devices performing cycles includes a cache controller and an external bus.
Claim 20
Dependent Claim
59 words
The method of claim 17, wherein said step of determining to keep asserted or to deassert is performed for all but said data read burst cycles followed by cache cycles and code read burst cycles followed by cache cycles and for those cases said row address strobe signal is deasserted and said dynamic random access memory devices are precharged.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |