Sense amplifier for a multiport memory and method

Claim 2

A sense amplifier for a memory comprising: two input ports for receiving input signals; a control port for receiving a sense amplifier precharge/strobe signal which either precharges or strobes said sense amplifier depending on a state of the precharge/strobe signal; two output ports for providing output signals from the sense amplifier, each of said two output ports having a precharge transistor which is turned on when the precharge/strobe signal is in the precharge state and an output buffer for isolating the sense amplifier from a capacitance difference between said two output ports; an output driver connected to said two output ports for providing a high impedance output state when said two output ports are low and for providing an output when one of said two output ports is high; an equalizing transistor for reducing a voltage difference between inputs to said output buffers when the sense amplifier precharge/strobe signal is received at said control port; and two cross-coupled amplifier load stages connected between inputs to said output buffers, said equalizing transistor being connected to inputs to said cross-coupled amplifier load stages.

Claim 3

The sense amplifier of claim 1 wherein said equalizing transistor gate and each said precharge transistor gate are connected to said control port so that said equalizing transistor and said precharge transistors are on when the sense amplifier precharge/strobe signal is received at said control port in the precharge state.

Claim 4

The sense amplifier of claim 1 wherein said two input ports are associated with a bitline and a bitline# in the memory.

Claim 5

The sense amplifier of claim 1 wherein both of the output signals are at the same state when the sense amplifier precharge/strobe signal is in the precharge state.

Claim 6

The sense amplifier of claim 1 wherein said output driver comprises an inverter having an input connected to one of said two output ports, a first conductivity type transistor having a gate connected to an output of said inverter, and a second conductivity type transistor having a gate connected to the other of said two output ports, said two transistors being connected in series with a node therebetween for providing a data output signal from between said two transistors.

Claim 7

A sense amplifier for a memory comprising: two output buffers each having an output port and a precharge transistor, one of said buffers at each of two sense amplifier outputs, for isolating the sense amplifier from a capacitance difference between the two output ports; an output driver connected to said two output ports for providing a high impedance output state when said two output ports are low and for providing an output when one of said two output ports is high, said output driver comprising, a first inverter having an input connected to one of said two output ports, a first transistor having a gate connected to an output of said first inverter, and a second transistor having a gate connected to the other of said two output ports, said first and second transistors being connected in series to provide a driver output signal from between said first and second transistors; and an equalizing transistor for reducing a voltage difference between inputs to said output buffers when a precharge/strobe signal is received at the sense amplifier and applied to a gate of said equalizing transistor and to a gate of each said precharge transistor, wherein the precharge/strobe signal is a single signal which is for either precharging or strobing depending on its state.

Claim 8

A sense amplifier for a memory comprising: two output buffers each having an output port and a precharge transistor, one of said buffers at each of two sense amplifier outputs, for isolating the sense amplifier from a capacitance difference between the two output ports; an output driver connected to said two output ports for providing a high impedance output state when said two output ports are low and for providing an output when one of said two output ports is high, said output driver comprising, a first inverter having an input connected to one of said two output ports, a first transistor having a gate connected to an output of said first inverter, and a second transistor having a gate connected to the other of said two output ports, said first and second transistors being connected in series to provide a driver output signal from between said first and second transistors; and an equalizing transistor for reducing a voltage difference between inputs to said output buffers when a precharge/strobe signal is received at the sense amplifier and applied to a gate of said equalizing transistor and to a gate of each said precharge transistor, wherein the precharge/strobe signal is a single signal which is for either precharging or strobing depending on its state.

Claim 9

The sense amplifier of claim 6 further comprising two cross-coupled amplifier load stages connected between inputs to said output buffers.

Claim 10

The sense amplifier of claim 6 further comprising a control port for receiving the precharge/strobe signal, and wherein said equalizing transistor gate and each said precharge transistor gate are connected to said control port so that said equalizing transistor and each said precharge transistor are on when the precharge/strobe signal is received at said control port in the precharge state.

Claim 11

The sense amplifier of claim 6 wherein both of the output signals are at the same state when the precharge/strobe signal is in the precharge state.

Claim 12

The sense amplifier of claim 6 in an integrated circuit.

Claim 15

The method of claim 11 wherein the step of providing signals from the output ports to an output driver comprises the steps of providing one of the signals from the output ports to an inverter, providing the inverter output to a gate of first transistor, providing the other of the signals from the output ports to a gate of a second transistor which is connected in series with the first transistor, and providing a data output signal from between the first and second transistors.

Claim 16

The method of claim 11 further comprising the steps of connecting two cross-coupled amplifier load stages between inputs to the output buffers.

Claim 17

The method of claim 11 wherein both of the output signals of the output buffers are at a first state when the precharge/strobe signal is in the precharge state.

Claim 18

A sense amplifier for a memory comprising: input ports for receiving input signals; two output ports for providing output signals from the sense amplifier; an output driver connected to said two output ports for providing a high impedance output state when said two output ports are low and for providing an output when one of said two output ports is high, said output driver comprising, a first inverter having an input connected to one of said two output ports, a first transistor having a gate connected to an output of said first inverter, and a second transistor having a gate connected to the other of said two output ports, said first and second transistors being connected in series to provide a driver output signal from between said first and second transistors; and a control port for receiving a sense amplifier precharge/strobe signal which either precharges or strobes said sense amplifier depending on a state of the precharge/strobe signal.

Claim 19

A sense amplifier for a memory comprising: input ports for receiving input signals; two output ports for providing output signals from the sense amplifier; an output driver connected to said two output ports for providing a high impedance output state when said two output ports are low and for providing an output when one of said two output ports is high, said output driver comprising, a first inverter having an input connected to one of said two output ports, a first transistor having a gate connected to an output of said first inverter, and a second transistor having a gate connected to the other of said two output ports, said first and second transistors being connected in series to provide a driver output signal from between said first and second transistors; and a control port for receiving a sense amplifier precharge/strobe signal which either precharges or strobes said sense amplifier depending on a state of the precharge/strobe signal.

Claim 20

The sense amplifier of claim 15 wherein each of said output ports further comprise a precharge transistor which is turned on when the precharge/strobe signal is in the precharge state and an output buffer for isolating the sense amplifier from a capacitance difference between said output ports.

Claim 21

The sense amplifier of claim 16 further comprising an equalizing transistor for reducing a voltage difference between inputs to said output buffers when the sense amplifier precharge/strobe signal is received at said control port.

Claim 22

The sense amplifier of claim 15 wherein each of said output ports further comprise a precharge means responsive to the precharge/strobe signal and a means for isolating the sense amplifier from capacitive differences between said output ports.

Claim 23

The sense amplifier of claim 18 further comprising a means reducing a voltage differential between inputs to said isolating means responsive to the precharge/strobe signal.