Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate

Claim 2

A floating gate type field effect transistor fabricated on a semiconductor substrate, comprising: a source region formed in a surface portion of said semiconductor substrate; a drain region formed in another surface portion of said semiconductor substrate, and spaced from said source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer covering said channel region, a floating gate electrode formed of p-type semiconductor material patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer covering said floating gate electrode, and a control gate electrode formed on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 3

The floating gate type field effect transistor as set forth in claim 1, in which said p-type semiconductor material is polysilicon doped with p-type dopant impurity.

Claim 4

The floating gate type field effect transistor as set forth in claim 1, in which said first gate insulating layer is formed of silicon oxide.

Claim 5

The floating gate type field effect transistor as set forth in claim 1, in which said first gate insulating layer is formed of silicon nitride.

Claim 6

The floating gate type field effect transistor as set forth in claim 1, in which said electrons are evacuated to said semiconductor substrate.

Claim 7

The floating gate type field effect transistor as set forth in claim 1, in which said source region is partially overlapped with said gate structure for evacuating said electrons to said source region.

Claim 8

A transistor according to claim 1, and further comprising, a pulse signal source adapted to apply said erasing pulse signal to said control gate electrode.

Claim 9

A floating gate type field effect transistor fabricated on a semiconductor substrate, comprising: a source region formed in a surface portion of said semiconductor substrate; a drain region formed in another surface portion of said semiconductor substrate, and spaced from said source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer covering said channel region, a floating gate electrode formed of p-type polysilicon doped with p-type dopant impurity, patterned on said first gate insulating layer and accumulating electrons in a write-in operation, a concentration of said p-type dopant impurity being equal to or greater than 5×10 16 cm -3 so as to produce an avalanche breakdown, a second gate insulating layer covering said floating gate electrode, and a control gate electrode formed on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 10

A floating gate type field effect transistor fabricated on a semiconductor substrate, comprising: a source region formed in a surface portion of said semiconductor substrate; a drain region formed in another surface portion of said semiconductor substrate, and spaced from said source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer covering said channel region, a floating gate electrode formed of p-type polysilicon doped with p-type dopant impurity, patterned on said first gate insulating layer and accumulating electrons in a write-in operation, a concentration of said p-type dopant impurity being equal to or greater than 5×10 16 cm -3 so as to produce an avalanche breakdown, a second gate insulating layer covering said floating gate electrode, and a control gate electrode formed on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 11

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer of silicon oxide covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said p-type silicon substrate and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 12

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer of silicon oxide covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said p-type silicon substrate and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 13

A transistor according to claim 9, and further comprising, a pulse signal source adapted to apply said erasing pulse signal to said control gate electrode.

Claim 14

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer of silicon nitride covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said p-type silicon substrate and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 15

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and having a first gate insulating layer of silicon nitride covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said p-type silicon substrate and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 16

A transistor according to claim 11, and further comprising, a pulse signal source adapted to apply said erasing pulse signal to said control gate electrode.

Claim 17

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and partially overlapping said heavily-doped n-type source region, said gate structure having a first gate insulating layer of silicon oxide covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said heavily doped p-type source region and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 18

A floating gate type field effect transistor fabricated on a p-type silicon substrate, comprising: a heavily doped n-type source region formed in a surface portion of said p-type silicon substrate; a heavily doped n-type drain region formed in another surface portion of said p-type silicon substrate, and spaced from said heavily doped n-type source region; a channel region located between said source region and said drain region; a gate structure provided on said channel region, and partially overlapping said heavily-doped n-type source region, said gate structure having a first gate insulating layer of silicon oxide covering said channel region, a floating gate electrode formed of p-type polysilicon patterned on said first gate insulating layer, and accumulating electrons in a write-in operation, a second gate insulating layer of silicon oxide covering said floating gate electrode, and a control gate electrode formed of n-type polysilicon patterned on said second gate insulating layer; and means for connecting said control gate electrode to a variable voltage source for generating a negative erasing pulse signal applied to said control gate electrode in an erasing operation, said negative erasing pulse signal causing said electrons to drift in a depletion layer produced in said floating gate electrode toward said first gate insulating layer, so as to exceed a potential gap between said floating gate electrode and said first gate insulating layer, thereby evacuating said electrons into said heavily doped p-type source region and preventing said first gate insulating layer from being damaged due to Fowler-Nordheim tunneling current.

Claim 19

A transistor according to claim 13, and further comprising, a pulse signal source adapted to apply said erasing pulse signal to said control gate electrode.