US5649213A — Method and apparatus for reducing power consumpti…

Claim 1

Independent Claim 212 words

A computer system with power management comprising: a central processing unit, said central processing unit having an active mode wherein it is responsive to external events, and a standby mode wherein power is maintained to said central processing unit and said central processing unit is in a low power state and is not responsive to said external events, said central processing unit operative such that whenever said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step, said central processing unit sets a condition indicating that said central processing unit is currently not required; and a power management circuit coupled to said central processing unit, said power management circuit being operative to monitor for said external events when said central processing unit is in said standby mode, and to cause said central processing unit to enter said active mode upon the detection of an external event, said power management circuit being operative to force said central processing unit into said standby mode in response to the condition indicating that said central processing unit is currently not required, said power management circuit being operative to control power applied to at least one peripheral device.

Claim 2

Dependent Claim 212 words

A computer system with power management comprising: a central processing unit, said central processing unit having an active mode wherein it is responsive to external events, and a standby mode wherein power is maintained to said central processing unit and said central processing unit is in a low power state and is not responsive to said external events, said central processing unit operative such that whenever said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step, said central processing unit sets a condition indicating that said central processing unit is currently not required; and a power management circuit coupled to said central processing unit, said power management circuit being operative to monitor for said external events when said central processing unit is in said standby mode, and to cause said central processing unit to enter said active mode upon the detection of an external event, said power management circuit being operative to force said central processing unit into said standby mode in response to the condition indicating that said central processing unit is currently not required, said power management circuit being operative to control power applied to at least one peripheral device.

Claim 3

Dependent Claim 69 words

A computer system as recited in claim 1 wherein said central processing unit has a standby input, and wherein said power management circuit has a standby output coupled to said standby input, said power management circuit being operative to enable said standby input to force said central processing unit into said standby mode, and to disable said standby input to force said central processing unit into said enabled mode.

Claim 4

Dependent Claim 61 words

A computer system as recited in claim 2 wherein said power management circuit is provided with a standby register, said standby register controlling said standby output and being coupled to said central processing unit by a bus, and wherein said central processing unit is operative to write to said standby register via said bus to force itself into said standby mode.

Claim 5

Dependent Claim 15 words

A computer system as recited in claim 1 wherein said external event includes an interrupt.

Claim 6

Dependent Claim 18 words

A computer system as recited in claim 1 wherein said external event includes a direct memory access request.

Claim 7

Dependent Claim 26 words

A computer system as recited in claim 1 wherein said external event is selected from the group including an interrupt and a direct memory access request.

Claim 8

Dependent Claim 225 words

A computer system as recited in claim 1 wherein said power management circuit includes: a standby register having a content which indicates one of a standby mode and an active mode; logic coupled to said standby register to produce a standby enabling output signal when said content of said standby register indicates a standby mode, and to produce a standby disabling output signal when said content of said standby register indicates an active mode; an external event input; logic coupled to said external event input and said standby register, said logic being operative to force said content of said standby register to said active mode upon the input of an external event; a register input coupled to said standby register, said register input being operative to write a content to said standby register which indicates said standby mode; a plurality of device registers associated with a plurality of peripheral devices, wherein contents of said device registers controls the power applied to said associated plurality of peripheral devices, each of said device registers including a peripheral portion and a power portion, where said power portions of said device registers are operative to control power switches for said devices; and an input address bus and a decoder for decoding said input address bus and for enabling one of said standby register and said plurality of device registers.

Claim 9

Dependent Claim 43 words

A computer system as recited in claim 7 wherein said power management circuit further includes a multiplexer having a plurality of inputs coupled to said standby register and said plurality of device registers, said multiplexer having an output coupled to a data bus.

Claim 10

Dependent Claim 274 words

A power management circuit comprising: a standby register having a content which indicates one of a standby mode and an active mode; logic coupled to said standby register to produce a standby enabling output signal when said content of said standby register indicates a standby mode, and to produce a standby disabling output signal when said content of said standby register indicates an active mode; an external event input; logic coupled to said external event input and said standby register, said logic being operative to force said content of said standby register to said active mode upon the input of an external event; a register input coupled to said standby register, said register input being operative to write a content to said standby register which indicates said standby mode; a plurality of device registers associated with a plurality of peripheral devices, wherein contents of said device registers control the power applied to said associated plurality of peripheral devices, each of said device registers including a peripheral portion and a power portion, where said power portions of said device registers are operative to control power switches for said devices; device power conservation logic coupled to said standby register, said devices, and said plurality of device registers, said device power conservation logic being operative to write content to said power portions of said device registers such that when a particular device is not in use, the corresponding power portion operates to turn off power to said particular device; and an input address bus and a decoder for decoding said input address bus and for enabling one of said standby register and said plurality of device registers.

Claim 11

Dependent Claim 274 words

A power management circuit comprising: a standby register having a content which indicates one of a standby mode and an active mode; logic coupled to said standby register to produce a standby enabling output signal when said content of said standby register indicates a standby mode, and to produce a standby disabling output signal when said content of said standby register indicates an active mode; an external event input; logic coupled to said external event input and said standby register, said logic being operative to force said content of said standby register to said active mode upon the input of an external event; a register input coupled to said standby register, said register input being operative to write a content to said standby register which indicates said standby mode; a plurality of device registers associated with a plurality of peripheral devices, wherein contents of said device registers control the power applied to said associated plurality of peripheral devices, each of said device registers including a peripheral portion and a power portion, where said power portions of said device registers are operative to control power switches for said devices; device power conservation logic coupled to said standby register, said devices, and said plurality of device registers, said device power conservation logic being operative to write content to said power portions of said device registers such that when a particular device is not in use, the corresponding power portion operates to turn off power to said particular device; and an input address bus and a decoder for decoding said input address bus and for enabling one of said standby register and said plurality of device registers.

Claim 12

Dependent Claim 39 words

A power management circuit as recited in claim 9 further comprising a multiplexer having a plurality of inputs coupled to said standby register and said plurality of device registers, said multiplexer having an output coupled to a data bus.

Claim 13

Dependent Claim 25 words

A power management circuit as recited in claim 9 wherein said external event is selected from the group including interrupts and direct memory access requests.

Claim 14

Independent Claim 237 words

A method for managing the power consumed by a computer system comprising the steps of: providing a central processing unit for responding to external events, said central processing unit being further responsive to a standby signal when in an active mode, said central processing unit entering a standby mode in response to said standby signal, said central processing unit setting a condition indicating that said central processing unit is currently not required whenever said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step; providing a power management circuit for responding to said external events when said central processing unit is in said standby mode and to cause said central processing unit to enter said active mode upon a detection of an external event, said power management circuit further operative to generate said standby signal in response to the condition indicating that said central processing unit is currently not required; and providing at least one peripheral device coupled to said power management circuit, wherein said power management circuit controls power to said peripheral device by powering on said peripheral device when a driver for said peripheral device is loaded by said central processing unit when said central processing unit is in said active mode and powering down said peripheral device when said peripheral device is not in use.

Claim 15

Independent Claim 237 words

A method for managing the power consumed by a computer system comprising the steps of: providing a central processing unit for responding to external events, said central processing unit being further responsive to a standby signal when in an active mode, said central processing unit entering a standby mode in response to said standby signal, said central processing unit setting a condition indicating that said central processing unit is currently not required whenever said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step; providing a power management circuit for responding to said external events when said central processing unit is in said standby mode and to cause said central processing unit to enter said active mode upon a detection of an external event, said power management circuit further operative to generate said standby signal in response to the condition indicating that said central processing unit is currently not required; and providing at least one peripheral device coupled to said power management circuit, wherein said power management circuit controls power to said peripheral device by powering on said peripheral device when a driver for said peripheral device is loaded by said central processing unit when said central processing unit is in said active mode and powering down said peripheral device when said peripheral device is not in use.

Claim 16

Dependent Claim 38 words

A method as recited in claim 12 wherein said step of providing a power management circuit further provides at least one device register, and a content of said device register controls the power applied to said peripheral device.

Claim 17

Dependent Claim 60 words

A method as recited in claim 13 wherein said step of providing a power management circuit further provides a plurality of device registers, and said step of providing at least one peripheral device comprises providing a plurality of peripheral devices coupled to said power management circuit, wherein contents of said device registers controls the power applied to associated peripheral devices.

Claim 18

Dependent Claim 23 words

A method as recited in claim 12 wherein said external event is selected from the group including interrupts and direct memory access requests.

Claim 19

Independent Claim 124 words

A method for managing power consumed by a computer system comprising the steps of: forcing a central processing unit of a computer system to enter a low-power standby mode when said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step; monitoring said computer system for external events to which said central processing unit should respond; reactivating said central processing unit to an active mode where said central processing unit is capable of responding to said external events; powering on a peripheral device when said peripheral device is requested for use; and powering down said peripheral device when said peripheral device is not in use.

Claim 20

Independent Claim 124 words

A method for managing power consumed by a computer system comprising the steps of: forcing a central processing unit of a computer system to enter a low-power standby mode when said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step; monitoring said computer system for external events to which said central processing unit should respond; reactivating said central processing unit to an active mode where said central processing unit is capable of responding to said external events; powering on a peripheral device when said peripheral device is requested for use; and powering down said peripheral device when said peripheral device is not in use.

Claim 21

Dependent Claim 63 words

A method as recited in claim 16 wherein said step of forcing a central processing unit of a computer system comprises the steps of: said central processing unit writing a standby command to a standby register of a power management circuit which functions independently of said central processing unit; and said power management circuit enabling a standby input of said central processing unit.

Claim 22

Dependent Claim 48 words

A method as recited in claim 17 wherein said step of monitoring said computer system comprises the steps of: said power management circuit detecting at least one of an interrupt and a direct memory access request; and writing an activate command to said standby register upon said detection.

Claim 23

Dependent Claim 37 words

A method as recited in claim 18 wherein said step of reactivating said central processing unit to a full-power mode comprises the step of said power management circuit disabling said standby input of said central processing unit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-07-14	2001-01-13	2001-07-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-07-14	2005-01-13	2005-07-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-07-14	2009-01-13	2009-07-15	$7700.00	Window Closed / Lapsed

Method and apparatus for reducing power consumption in a computer system

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