Digital computing system with low power mode and special bus cycle therefor

Claim 1

An integrated circuit computing system comprising: a central processing unit further comprising: a clock signal input terminal; an interrupt signal input terminal; first register means for storing an interrupt mask value; first comparator means coupled to receive a regular, periodic clock signal from the clock signal input terminal for comparing a priority level of an interrupt signal received at the interrupt signal input terminal to the interrupt mask value, the first comparator means functions only while a regular, periodic clock signal is being received at the clock signal input terminal; execution means for executing instructions only while a regular, periodic clock signal is received at the clock signal input terminal and for executing no instructions at all while no regular, .periodic dock signal is received at the clock signal input terminal, the execution means further comprises means for executing a first instruction and for generating a first control signal only when the first instruction is executed; and a bus interface means having a plurality of bus interface terminals including address terminals and data terminals, the bus interface is coupled to receive the first control signal from the execution means, the bus interface means is for placing signals indicative of the interrupt mask value onto a portion of the plurality of bus interface terminals only when the first control signal is received from the execution means; an internal bus having address lines coupled to the address terminals of the bus interface of the central processing unit and having data lines coupled to the data terminals of the bus interface of the central processing unit; an integration module having a first plurality of bus interface terminals including internal address terminals and internal data terminals coupled, respectively, to the address lines and data lines of the internal bus and having a plurality of external interface terminals for coupling the integrated circuit computing system to devices external to the integrated circuit computing system, the integration module further comprising: a clock signal generator means coupled to a first clock signal output terminal of the integration module, the first clock signal output terminal of the integration module is coupled to the clock signal input terminal of the central processing unit, the clock signal generator further comprises means for providing a regular, periodic clock signal to the first clock signal output terminal of the integration module and, thereby, to the clock signal input terminal of the central processing unit and for ceasing to provide the regular, periodic clock signal to the first clock signal output terminal of the integration module when the bus interface means of the central processing unit has placed the signals indicative of the interrupt mask value onto the portion of the plurality of bus interface terminals and for resuming providing the clock signal to the first clock signal output terminal of the integration module when a second control signal is received; second register means coupled to the first plurality of bus interface terminals of the integration module for receiving, only in response to the first control signal, the signals indicative of the interrupt mask value from the first plurality of bus interface terminals and for thereafter storing the signals indicative of the interrupt mask value; second comparator means for comparing a priority level of an interrupt signal to the signals stored in the second register means and for conditionally providing the second control signal to the clock signal generator based upon the outcome of comparing a priority level of an interrupt signal to the signals stored in the second register means, the second comparator means is active only after the bus interface means of the central processing unit has placed the signal indicative of the interrupt mask value onto the portion of the plurality of bus interface terminals of the central processing unit and until the second control signal has been produced.