US5648973A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I/O toggle test method using JTAG
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-02-06
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Granted: 1997-07-15
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Expires: 2016-02-06
Abstract
Abstract A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. The test pattern of alternating data bits is then latched to the JTAG data latch register and driven onto the output pins of the IC chip. The bidirectional buffers connected to the output pins are then enabled for output while the IC tester tri-states its alternating data test pattern. The test pattern is then shifted by one bit within the IC's JTAG shift register and parallel loaded into the JTAG latch register on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip. The process is then repeated once more to provide an alternating transition for each of the output pins so that a toggle from high to low and also from low to high is satisfied for each of the output pins on the IC chip.
Inventors
- 👤 L. Randall Mote, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
211 words
A method for quickly and efficiently toggling output pins under test on an integrated circuit, wherein each of said output pins is coupled to a corresponding boundary scan latch, and each of said boundary scan latches is coupled to a corresponding boundary scan shift register element, and wherein said output pins are further in electrical communication with a test circuit, said method comprising the steps of: parallel loading, via said output pins, a first test vector from the test circuit into said boundary scan shift register elements as a first test pattern; placing said test circuit in a high impedance state; driving said first test pattern onto said output pins from said boundary scan latches in response to said first test vector; parallel loading said first test pattern into said boundary scan shift register elements from said output pins; driving a second test pattern onto said output pins from said boundary scan latches, wherein said second test pattern is the complement of said first test pattern; parallel loading said second test pattern into said boundary scan shift register elements from said output pins; and driving a third test pattern onto said output pins from said boundary scan latches, wherein said third test pattern is the complement of said second test pattern.
Claim 2
Independent Claim
211 words
A method for quickly and efficiently toggling output pins under test on an integrated circuit, wherein each of said output pins is coupled to a corresponding boundary scan latch, and each of said boundary scan latches is coupled to a corresponding boundary scan shift register element, and wherein said output pins are further in electrical communication with a test circuit, said method comprising the steps of: parallel loading, via said output pins, a first test vector from the test circuit into said boundary scan shift register elements as a first test pattern; placing said test circuit in a high impedance state; driving said first test pattern onto said output pins from said boundary scan latches in response to said first test vector; parallel loading said first test pattern into said boundary scan shift register elements from said output pins; driving a second test pattern onto said output pins from said boundary scan latches, wherein said second test pattern is the complement of said first test pattern; parallel loading said second test pattern into said boundary scan shift register elements from said output pins; and driving a third test pattern onto said output pins from said boundary scan latches, wherein said third test pattern is the complement of said second test pattern.
Claim 3
Dependent Claim
15 words
A method as defined in claim 1, wherein said test circuit comprises an IC tester.
Claim 4
Dependent Claim
41 words
A method as defined in claim 1, wherein said first test pattern is shifted within said boundary scan shift register elements after parallel loading said first test pattern into said boundary scan shift register elements to produce said second test pattern.
Claim 5
Dependent Claim
41 words
A method as defined in claim 1, wherein said second test pattern is shifted within said boundary scan shift register elements after parallel loading said second test pattern into said boundary scan shift register elements to produce said third test pattern.
Claim 6
Dependent Claim
37 words
A method as defined in claim 1, wherein the test circuit drives a complement test pattern after loading said first test vector into said boundary scan shift register elements before being placed in said high impedance state.
Claim 7
Independent Claim
287 words
An apparatus for quickly and efficiently toggling output pins under test on an integrated circuit, wherein each of said output pins electrically connects to a corresponding boundary scan latch, and each of said boundary scan latches electrically connects to a corresponding boundary scan shift register element, and wherein said output pins are further in electrical communication with a test circuit, said apparatus comprising: a boundary scan shift register comprising a plurality of said boundary scan shift register elements connected in a daisy-chain configuration to enable data to be shifted from one element to a next adjacent element, said boundary scan shift register receiving a parallel loaded test pattern from said output pins, said parallel loaded test pattern comprising alternating logical ones and logical zeroes; and a multiplexer situated at an end of said boundary scan shift register, wherein said multiplexer has a first input in communication with an internal test data input (TDI) line, and a second input in communication with an inverted output of a first boundary scan shift register element of said boundary scan shift register, said output of said multiplexer in communication with an input of said first boundary scan shift register element, wherein said multiplexer causes said inverted output of said first boundary scan shift register element to be input to said input of said first boundary scan shift register element when said multiplexer is in a toggle test mode, and wherein said parallel loaded test pattern in said elements of said boundary scan shift register is logically shifted by one element after loading said parallel loaded test pattern of alternating logical ones and logical zeroes, thereby forming a pattern complementary to said parallel loaded test pattern in said boundary scan shift register.
Claim 8
Independent Claim
287 words
An apparatus for quickly and efficiently toggling output pins under test on an integrated circuit, wherein each of said output pins electrically connects to a corresponding boundary scan latch, and each of said boundary scan latches electrically connects to a corresponding boundary scan shift register element, and wherein said output pins are further in electrical communication with a test circuit, said apparatus comprising: a boundary scan shift register comprising a plurality of said boundary scan shift register elements connected in a daisy-chain configuration to enable data to be shifted from one element to a next adjacent element, said boundary scan shift register receiving a parallel loaded test pattern from said output pins, said parallel loaded test pattern comprising alternating logical ones and logical zeroes; and a multiplexer situated at an end of said boundary scan shift register, wherein said multiplexer has a first input in communication with an internal test data input (TDI) line, and a second input in communication with an inverted output of a first boundary scan shift register element of said boundary scan shift register, said output of said multiplexer in communication with an input of said first boundary scan shift register element, wherein said multiplexer causes said inverted output of said first boundary scan shift register element to be input to said input of said first boundary scan shift register element when said multiplexer is in a toggle test mode, and wherein said parallel loaded test pattern in said elements of said boundary scan shift register is logically shifted by one element after loading said parallel loaded test pattern of alternating logical ones and logical zeroes, thereby forming a pattern complementary to said parallel loaded test pattern in said boundary scan shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |