Patent US5648277A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5648277A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device

Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1994-11-02
•
Granted: 1997-07-15
•
Expires: 2014-11-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor layer, forming a gate electrode on the insulating film, pattering the first insulating film into a second insulating film so that a portion of the semiconductor layer is exposed while the second insulating film has extensions which extend beyond the side edges of the gate electrode, and performing ion introduction for forming impurity regions using the gate electrode and extensions of the gate insulating film as a mask. The condition of the ion introduction is varied in order to control the regions of the semiconductor layer to be added with the impurity and the concentration of the impurity therein.

Inventors

  • 👤 Hongyong Zhang
  • 👤 Naoaki Yamaguchi
  • 👤 Yasuhiko Takemura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D86/00; H10D86/40; H10D86/471; H10D86/60

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 154 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on an insulating surface; forming a first insulating film on said semiconductor layer; forming a gate electrode on said first insulating film; forming a first anodic oxide film on side surfaces of said gate electrode by applying an electric current to said gate electrode in an electrolyte; etching said first insulating film in order to thin or remove said insulating film using said first anodic oxide film as a mask, thereby forming a gate insulating film; removing said first anodic oxide film after said etching; and introducing ions of an impurity of an N or P type conductivity into a portion of said semiconductor layer using said gate electrode and said gate insulating film as a mask, wherein said introducing is carried out with at least two different conditions having a higher acceleration voltage and a lower acceleration voltage.
Claim 2
Independent Claim 154 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on an insulating surface; forming a first insulating film on said semiconductor layer; forming a gate electrode on said first insulating film; forming a first anodic oxide film on side surfaces of said gate electrode by applying an electric current to said gate electrode in an electrolyte; etching said first insulating film in order to thin or remove said insulating film using said first anodic oxide film as a mask, thereby forming a gate insulating film; removing said first anodic oxide film after said etching; and introducing ions of an impurity of an N or P type conductivity into a portion of said semiconductor layer using said gate electrode and said gate insulating film as a mask, wherein said introducing is carried out with at least two different conditions having a higher acceleration voltage and a lower acceleration voltage.
Claim 3
Dependent Claim 29 words
The method of claim 1 wherein a dose amount during said introducing step with said higher acceleration voltage is smaller than a dose amount with said lower acceleration voltage.
Claim 4
Dependent Claim 20 words
The method of claim 1 further comprising the step of activating said impurity by light irradiation after said introducing step.
Claim 5
Dependent Claim 22 words
The method of claim 1 further comprising the step of removing a portion of said gate insulating film after said introducing step.
Claim 6
Independent Claim 189 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on an insulating surface; forming an insulating film on an entire surface of said semiconductor layer; forming a gate electrode on said insulating film; patterning said insulating film into a gate insulating film in such a manner that said gate insulating film extends beyond side edges of said gate electrode but does not completely cover said semiconductor layer so that portions of said semiconductor layer are exposed; and introducing one conductivity type impurity ions into said semiconductor layer using said gate electrode and said gate insulating layer as a mask, wherein a condition of said introducing step is selected so that regions of said semiconductor layer located below extensions of said gate insulating film beyond said gate electrode are added with said impurity at a first concentration while exposed regions of said semiconductor layer are added with said impurity at a second concentration which is different from said first concentration, wherein said insulating film is patterned by using a mask which is an anodic oxide film formed on side surfaces of said gate electrode.
Claim 7
Independent Claim 189 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on an insulating surface; forming an insulating film on an entire surface of said semiconductor layer; forming a gate electrode on said insulating film; patterning said insulating film into a gate insulating film in such a manner that said gate insulating film extends beyond side edges of said gate electrode but does not completely cover said semiconductor layer so that portions of said semiconductor layer are exposed; and introducing one conductivity type impurity ions into said semiconductor layer using said gate electrode and said gate insulating layer as a mask, wherein a condition of said introducing step is selected so that regions of said semiconductor layer located below extensions of said gate insulating film beyond said gate electrode are added with said impurity at a first concentration while exposed regions of said semiconductor layer are added with said impurity at a second concentration which is different from said first concentration, wherein said insulating film is patterned by using a mask which is an anodic oxide film formed on side surfaces of said gate electrode.
Claim 8
Dependent Claim 11 words
The method of claim 5 wherein said semiconductor layer comprises silicon.
Claim 9
Dependent Claim 18 words
The method of claim 6 wherein said impurity is selected from the group consisting of phosphorous and boron.

References Cited (Backward Citations)

JPS5470762A Cited
US4232327A Cited
JPS6055665A Cited
JPS61224360A Cited
US4728617A Cited
US5100810A Cited
US5292675A Cited
JPH05275448A Cited
JPH0613397A Cited
US5508209A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-07-14 2001-01-13 2001-07-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-07-14 2005-01-13 2005-07-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-07-14 2009-01-13 2009-07-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag