US5646060A
Expired / Lapsed
US
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Method for making an EEPROM cell with isolation transistor
Assignee: NXP USA Inc
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Filing: 1995-05-30
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Granted: 1997-07-08
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Expires: 2015-05-30
Abstract
Abstract An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
Inventors
- 👤 Ko-Min Chang
- 👤 Danny Pak-Chum Shum
- 👤 Kuo-Tung Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:20
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
79 words
A method for making an electrically erasable and programmable memory cell, comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; depositing and patterning a first conductive layer on the tunnel dielectric to form an isolation gate and a floating gate on the tunnel dielectric; forming an interlayer dielectric over the isolation gate and floating gate; and depositing and patterning a second conductive layer to form a control gate overlying the floating gate.
Claim 2
Independent Claim
79 words
A method for making an electrically erasable and programmable memory cell, comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; depositing and patterning a first conductive layer on the tunnel dielectric to form an isolation gate and a floating gate on the tunnel dielectric; forming an interlayer dielectric over the isolation gate and floating gate; and depositing and patterning a second conductive layer to form a control gate overlying the floating gate.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein the step of forming a tunnel dielectric comprises forming a tunnel oxide having a thickness of less than approximately 120 angstroms.
Claim 4
Dependent Claim
155 words
The method of claim 1 wherein the isolation gate has a first side and an opposing second side and wherein the floating gate has a first side and a second side, and further comprising the steps of: forming a first doped region in the substrate approximately aligned to the first side of the isolation gate; forming a second doped region in the substrate between the isolation gate and the floating gate and approximately aligned to the second side of the isolation gate and the first side of the floating gate; and forming a third doped region in the substrate approximately aligned to the second side of the floating gate; wherein the first doped region is a source of an isolation transistor; wherein the second doped region is a drain of the isolation transistor and a source of a floating gate transistor; and wherein the third doped region is a drain of the floating gate transistor.
Claim 5
Dependent Claim
29 words
The method of claim 3 wherein the tunnel dielectric is an only dielectric separating the isolation gate and the floating gate from the semiconductor substrate within the memory cell.
Claim 6
Dependent Claim
27 words
The method of claim 1 wherein the step of forming a tunnel dielectric comprises forming a tunnel dielectric having a substantially uniform thickness within the memory cell.
Claim 7
Independent Claim
127 words
A method for making an electrically erasable and programmable memory cell comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric having a substantially uniform thickness on the semiconductor substrate; forming a first gate electrode and a second gate electrode on the tunnel dielectric, wherein the first gate electrode and the second gate electrode are separated from the semiconductor substrate only by the tunnel dielectric within the memory cell; doping the semiconductor substrate to form a first source region and a first drain region associated with the first gate electrode and a second source region and a second drain region associated with the second gate electrode; and forming a third gate electrode overlying the second gate electrode, and being separated therefrom by a dielectric material.
Claim 8
Independent Claim
127 words
A method for making an electrically erasable and programmable memory cell comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric having a substantially uniform thickness on the semiconductor substrate; forming a first gate electrode and a second gate electrode on the tunnel dielectric, wherein the first gate electrode and the second gate electrode are separated from the semiconductor substrate only by the tunnel dielectric within the memory cell; doping the semiconductor substrate to form a first source region and a first drain region associated with the first gate electrode and a second source region and a second drain region associated with the second gate electrode; and forming a third gate electrode overlying the second gate electrode, and being separated therefrom by a dielectric material.
Claim 9
Dependent Claim
24 words
The method of claim 6 wherein the step of forming a tunnel dielectric comprises thermally growing a silicon dioxide layer on the semiconductor substrate.
Claim 10
Dependent Claim
28 words
The method of claim 6 wherein the step of forming a tunnel dielectric comprises forming a tunnel dielectric having a substantially uniform thickness of less than 120 angstroms.
Claim 11
Dependent Claim
51 words
The method of claim 6 wherein the step of forming a first gate electrode and a second gate electrode comprises forming a floating gate electrode as the second gate electrode, and wherein the step of forming a third gate electrode comprises forming a control gate electrode as the third gate electrode.
Claim 12
Dependent Claim
34 words
The method of claim 6 wherein the step of doping the semiconductor substrate comprises doping such that the first drain region and the second source region occupy a same area of the semiconductor substrate.
Claim 13
Dependent Claim
65 words
The method of claim 6 wherein the step of doping the semiconductor substrate comprises doping the semiconductor substrate to form a first source region and a first drain region which are both self-aligned relative to the first gate electrode, and doping the semiconductor substrate to form a second source region and a second drain region which are both self-aligned relative to the second gate electrode.
Claim 14
Independent Claim
131 words
A method for making an electrically erasable and programmable memory cell comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate having a substantially uniform thickness of less than 120 angstroms; depositing a first polysilicon layer on the tunnel dielectric; patterning the first polysilicon layer to form an isolation gate electrode of an isolation transistor and a floating gate electrode of a floating gate transistor on the tunnel dielectric; forming source and drain regions for the isolation transistor and for the floating gate transistor in the semiconductor substrate; forming an interpoly dielectric layer over the floating gate electrode; depositing a second polysilicon layer over the interpoly dielectric layer; and patterning the second polysilicon layer to form a control gate electrode of the floating gate transistor.
Claim 15
Independent Claim
131 words
A method for making an electrically erasable and programmable memory cell comprising the steps of: providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate having a substantially uniform thickness of less than 120 angstroms; depositing a first polysilicon layer on the tunnel dielectric; patterning the first polysilicon layer to form an isolation gate electrode of an isolation transistor and a floating gate electrode of a floating gate transistor on the tunnel dielectric; forming source and drain regions for the isolation transistor and for the floating gate transistor in the semiconductor substrate; forming an interpoly dielectric layer over the floating gate electrode; depositing a second polysilicon layer over the interpoly dielectric layer; and patterning the second polysilicon layer to form a control gate electrode of the floating gate transistor.
Claim 16
Dependent Claim
80 words
The method of claim 12 wherein the step of forming source and drain regions comprises, forming a first doped region in the semiconductor substrate to serve as a source of the isolation transistor, forming a second doped region in the semiconductor substrate to serve as a drain of the isolation transistor and as a source of the floating gate transistor, and forming a third doped region in the semiconductor substrate to serve as a drain of the floating gate transistor.
Claim 17
Dependent Claim
36 words
The method of claim 13 wherein the first and the second doped regions are self-aligned relative to the isolation gate electrode and the second and the third doped regions are self-aligned relative to floating gate electrode.
Claim 18
Dependent Claim
22 words
The method of claim 12 wherein the step of forming a tunnel dielectric comprises thermally growing silicon dioxide on the semiconductor substrate.
Claim 19
Dependent Claim
45 words
The method of claim 12 wherein the isolation gate electrode and the floating gate electrode are formed such that the tunnel dielectric is an only dielectric which separates the isolation gate electrode and the floating gate electrode from the semiconductor substrate within the memory cell.
Claim 20
Dependent Claim
44 words
The method of claim 12 wherein the isolation gate electrode and the floating gate electrode are formed such that the isolation gate electrode and the floating gate electrode are separated from the semiconductor substrate only by the substantially uniform thickness of the tunnel dielectric.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |